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Performance enhancement of CMOS VLSI circuits by transistor reordering

Authors:

Bradley S. Carlson,

C. Y. Roger ChenAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 361 - 366

https://doi.org/10.1145/157485.164931

Published: 01 July 1993 Publication History

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References

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Cited By

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Ting-Wei Chiang Chen CWei-Yu Chen (2007)A technique for selecting CMOS transistor orders2007 25th International Conference on Computer Design10.1109/ICCD.2007.4601936(438-443)Online publication date: Oct-2007
https://doi.org/10.1109/ICCD.2007.4601936
Li PHajj I(2006)Computer-aided redesign of VLSI circuits for hot-carrier reliabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.50613315:5(453-464)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.506133
Hossain RZheng MAlbicki A(2006)Reducing power dissipation in CMOS circuits by signal probability based transistor reorderingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.48910715:3(361-368)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.489107
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Index Terms

Performance enhancement of CMOS VLSI circuits by transistor reordering
1. Hardware

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Ting-Wei Chiang Chen CWei-Yu Chen (2007)A technique for selecting CMOS transistor orders2007 25th International Conference on Computer Design10.1109/ICCD.2007.4601936(438-443)Online publication date: Oct-2007
https://doi.org/10.1109/ICCD.2007.4601936
Li PHajj I(2006)Computer-aided redesign of VLSI circuits for hot-carrier reliabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.50613315:5(453-464)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.506133
Hossain RZheng MAlbicki A(2006)Reducing power dissipation in CMOS circuits by signal probability based transistor reorderingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.48910715:3(361-368)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.489107
Carlson BLee S(2006)Delay optimization of digital CMOS VLSI circuits by transistor reorderingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.46633514:10(1183-1192)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.466335
Kong JOverhauser D(2006)Methods to improve digital MOS macromodel accuracyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.39173414:7(868-881)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.391734
Li PStamoulis GHajj I(2006)A probabilistic timing approach to hot-carrier effect estimationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.31746513:10(1223-1234)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.317465
Alexander MKahng ASarrafzadeh M(1997)Power optimization for FPGA look-up tablesProceedings of the 1997 international symposium on Physical design10.1145/267665.267707(156-162)Online publication date: 1-Apr-1997
https://dl.acm.org/doi/10.1145/267665.267707
Lefebvre MMarple DSechen CYoffa EDe Micheli GRabaey J(1997)The future of custom cell generation in physical synthesisProceedings of the 34th annual Design Automation Conference10.1145/266021.266196(446-451)Online publication date: 13-Jun-1997
https://dl.acm.org/doi/10.1145/266021.266196
Lefebvre MMarple D(1997)The Future Of Custom Cell Generation in Physical SynthesisProceedings of the 34th Design Automation Conference10.1109/DAC.1997.597189(446-451)Online publication date: 1997
https://doi.org/10.1109/DAC.1997.597189
Cong J(1997)Modeling and layout optimization of VLSI devices and interconnects in deep submicron designProceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference10.1109/ASPDAC.1997.600085(121-126)Online publication date: 1997
https://doi.org/10.1109/ASPDAC.1997.600085
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Transistor and pin reordering for leakage reduction in CMOS circuits

Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates

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