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Delay fault coverage and performance tradeoffs

Authors:

William K. Lam,

Alexander Saldanha,

Robert K. Brayton,

Alberto L. Sangiovanni-VincentelliAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 446 - 452

https://doi.org/10.1145/157485.164970

Published: 01 July 1993 Publication History

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References

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W. Lam, A. Saldanha, R. Brayton, and A. Sangiovanni- Vincentelli. Delay fault testing: Trading fault coverage, test set size, and performance, in Proceedings of the Symposium on Integrated Systems, Seattle - WA, March 1993.

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Cited By

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Taka EMaragos KLentaris GSoudris D(2021)Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/345884314:3(1-30)Online publication date: 12-Aug-2021
https://dl.acm.org/doi/10.1145/3458843
Reddy S(2009)Models for Delay FaultsModels in Hardware Testing10.1007/978-90-481-3282-9_3(71-103)Online publication date: 27-Oct-2009
https://doi.org/10.1007/978-90-481-3282-9_3
Chen YLiou J(2008)Diagnosis framework for locating failed segments of path delay faultsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200036716:6(755-765)Online publication date: 1-Jun-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2000367
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Index Terms

Delay fault coverage and performance tradeoffs

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The Total Delay Fault Model and Statistical Delay Fault Coverage

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Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults
ICCAD '96: Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

In this paper, we propose a new and realistic definition of delay fault coverage, based on the percentage of fabricated faulty chips which can be detected as faulty by a given test set. This metric takes into account the probability distribution of ...
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Transition path delay faults were defined to capture the behavior of both small and large delay defects in a single fault model. The number of detectable transition path delay faults as defined earlier is the same or close to the number of conventional ...

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993

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EDAC
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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Taka EMaragos KLentaris GSoudris D(2021)Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/345884314:3(1-30)Online publication date: 12-Aug-2021
Reddy S(2009)Models for Delay FaultsModels in Hardware Testing10.1007/978-90-481-3282-9_3(71-103)Online publication date: 27-Oct-2009
Chen YLiou J(2008)Diagnosis framework for locating failed segments of path delay faultsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200036716:6(755-765)Online publication date: 1-Jun-2008
Li JLach J(2007)Negative-skewed shadow registers for at-speed delay variation characterization2007 25th International Conference on Computer Design10.1109/ICCD.2007.4601924(354-359)Online publication date: Oct-2007
Sachdev MGyvez J(2007)Digital CMOS Fault ModelingDefect-Oriented Testing for Nano-Metric CMOS VLSI Circuits10.1007/0-387-46547-2_3(69-110)Online publication date: 2007
Wang (2007)System-on-Chip Test ArchitecturesundefinedOnline publication date: 20-Nov-2007
Tekumalla RMenon P(2006)Identification of primitive faults in combinational and sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.96943620:12(1426-1442)Online publication date: 1-Nov-2006
Sivaraman MStrojwas A(2006)Path delay fault diagnosis and coverage-a metric and an estimation techniqueIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.91376120:3(440-457)Online publication date: 1-Nov-2006
Sivaraman MStrojwas A(2006)Primitive path delay faultsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.89285819:11(1347-1362)Online publication date: 1-Nov-2006
Kishinevsky MKondratyev ALavagno LSaldanha ATaubin A(2006)Partial-scan delay fault testing of asynchronous circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.73619117:11(1184-1199)Online publication date: 1-Nov-2006
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Recommendations

The Total Delay Fault Model and Statistical Delay Fault Coverage

Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults

Hazard-based detection conditions for improved transition path delay fault coverage