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Sequential circuit test generation on a distributed system

Authors:

P. Agrawal,

V. D. Agrawal,

J. VilloldoAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 107 - 111

https://doi.org/10.1145/157485.164762

Published: 01 July 1993 Publication History

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References

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Cited By

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Corno FPrinetto PRebaudengo MSonza Reorda M(2006)GATTOIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.51157815:8(991-1000)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.511578
Wolf JKaufman LKlenke RAylor JWaxman R(2006)An analysis of fault partitioned parallel test generationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.50613915:5(517-534)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.506139
Corno FPrinetto PRebaudengo MReorda MVeiluva E(2006)A PVM tool for automatic test generation on parallel and distributed systemsHigh-Performance Computing and Networking10.1007/BFb0046607(39-44)Online publication date: 2-Feb-2006
https://doi.org/10.1007/BFb0046607
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Sequential circuit test generation on a distributed system

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Corno FPrinetto PRebaudengo MSonza Reorda M(2006)GATTOIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.51157815:8(991-1000)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.511578
Wolf JKaufman LKlenke RAylor JWaxman R(2006)An analysis of fault partitioned parallel test generationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.50613915:5(517-534)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.506139
Corno FPrinetto PRebaudengo MReorda MVeiluva E(2006)A PVM tool for automatic test generation on parallel and distributed systemsHigh-Performance Computing and Networking10.1007/BFb0046607(39-44)Online publication date: 2-Feb-2006
https://doi.org/10.1007/BFb0046607
Dahmen HGläser UVierhaus H(2005)Automatic test pattern generation with optimal load balancingParallel Virtual Machine — EuroPVM '9610.1007/3540617795_26(205-212)Online publication date: 8-Jul-2005
https://doi.org/10.1007/3540617795_26
Zhide Zeng Jihua Chen Pengxin Liu (1999)A fault partitioning method in parallel test generation for large scale VLSI circuitsProceedings Eighth Asian Test Symposium (ATS'99)10.1109/ATS.1999.810741(133-137)Online publication date: 1999
https://doi.org/10.1109/ATS.1999.810741
Prabhakaran PBanerjee P(1999)Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow GraphsIEEE Transactions on Computers10.1109/12.78088648:7(762-768)Online publication date: 1-Jul-1999
https://dl.acm.org/doi/10.1109/12.780886
Dahmen HGlaser UVierhaus H(1997)An efficient dynamic parallel approach to automatic test pattern generationProceedings Great Lakes Symposium on VLSI10.1109/GLSV.1997.580503(112-117)Online publication date: 1997
https://doi.org/10.1109/GLSV.1997.580503
Krauss PGanz AAntreich K(1997)Distributed Test Pattern Generation for Stuck-At Faults in Sequential CircuitsJournal of Electronic Testing: Theory and Applications10.1023/A:100826642238011:3(227-245)Online publication date: 1-Dec-1997
https://dl.acm.org/doi/10.1023/A%3A1008266422380
Klenke RAylor JWolf J(1996)An analysis of fault partitioning algorithms for fault partitioned ATPGProceedings of 14th VLSI Test Symposium10.1109/VTEST.1996.510862(231-239)Online publication date: 1996
https://doi.org/10.1109/VTEST.1996.510862
Ivanov A(1996)Design for testability and built-in self-test of integrated circuits and systems: how these can add value to your products38th Midwest Symposium on Circuits and Systems. Proceedings10.1109/MWSCAS.1995.510189(712-717)Online publication date: 1996
https://doi.org/10.1109/MWSCAS.1995.510189
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