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Reliable non-zero skew clock trees using wire width optimization

Authors:

Satyamurthy Pullela,

Noel Menezes,

Lawrence T. PillageAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 165 - 170

https://doi.org/10.1145/157485.164653

Published: 01 July 1993 Publication History

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Cited By

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Ryu Cho Han (2019)Timing Criticality-Aware Design Optimization using BEOL Air Gap Technology on Consecutive Metal LayersElectronics10.3390/electronics81112748:11(1274)Online publication date: 1-Nov-2019
https://doi.org/10.3390/electronics8111274
Guthaus M(2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-13
Kahng AKang SLee H(2013)Smart non-default routing for clock power reductionProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488846(1-7)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488846
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Reliable non-zero skew clock trees using wire width optimization

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Pulsed latches, latches driven by a brief clock pulse, offer the same convenience of timing verification and optimization as flip-flop-based circuits, while retaining the advantages of latches over flip-flops. But a pulsed latch that uses a single pulse ...

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993

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Sponsor:

EDAC
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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Ryu Cho Han (2019)Timing Criticality-Aware Design Optimization using BEOL Air Gap Technology on Consecutive Metal LayersElectronics10.3390/electronics81112748:11(1274)Online publication date: 1-Nov-2019
https://doi.org/10.3390/electronics8111274
Guthaus M(2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-13
Kahng AKang SLee H(2013)Smart non-default routing for clock power reductionProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488846(1-7)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488846
Guthaus MWilke GReis R(2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442102
Chi-Chou Kao Kun-Cte Lin (2013)Clock skew minimization with adjustable delay buffers restriction2013 International Symposium on Next-Generation Electronics10.1109/ISNE.2013.6512356(321-324)Online publication date: Feb-2013
https://doi.org/10.1109/ISNE.2013.6512356
Lung CZeng ZChou CChang SDe Micheli GAl-Hashimi BMueller WMacii E(2010)Clock skew optimization considering complicated power modesProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871280(1474-1479)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871280
Narasimhan ASridhar R(2010)Variability aware low-power delay optimal buffer insertion for global interconnectsIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2010.207379057:12(3055-3063)Online publication date: 1-Dec-2010
https://dl.acm.org/doi/10.1109/TCSI.2010.2073790
Ye XLi PLiu F(2010)Exact time-domain second-order adjoint-sensitivity computation for linear circuit analysis and optimizationIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2009.201572057:1(236-248)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TCSI.2009.2015720
Su YHon WYang CChang SChang Y(2010)Clock skew minimization in multi-voltage mode designs using adjustable delay buffersIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.206165429:12(1921-1930)Online publication date: 1-Dec-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2061654
Onaissi SHeloue KNajm F(2009)Clock skew optimization via wiresizing for timing sign-off covering all process cornersProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629964(196-201)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1629964
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Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing

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