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VIPER: an efficient vigorously sensitizable path extractor

Authors:

Hoon Chang,

Jacob A. AbrahamAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 112 - 117

https://doi.org/10.1145/157485.158845

Published: 01 July 1993 Publication History

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Jurimagi LUbar RJenihhin MRaik JDevadze SOyeniran A(2019)Application Specific True Critical Paths Identification in Sequential Circuits2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS.2019.8854442(299-304)Online publication date: Jul-2019
https://doi.org/10.1109/IOLTS.2019.8854442
Ubar RJurimagi LJenihhin MRaik JOlugbenga NViies V(2018)Timing-critical path analysis with structurally synthesized BDDs2018 7th Mediterranean Conference on Embedded Computing (MECO)10.1109/MECO.2018.8406051(1-6)Online publication date: Jun-2018
https://doi.org/10.1109/MECO.2018.8406051
Ubar RKostin SJenihhin MRaik J(2017)A scalable technique to identify true critical paths in sequential circuits2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS.2017.7934568(152-157)Online publication date: Apr-2017
https://doi.org/10.1109/DDECS.2017.7934568
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VIPER: an efficient vigorously sensitizable path extractor

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 July 1993

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IEEE-CAS

DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Jurimagi LUbar RJenihhin MRaik JDevadze SOyeniran A(2019)Application Specific True Critical Paths Identification in Sequential Circuits2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS.2019.8854442(299-304)Online publication date: Jul-2019
Ubar RJurimagi LJenihhin MRaik JOlugbenga NViies V(2018)Timing-critical path analysis with structurally synthesized BDDs2018 7th Mediterranean Conference on Embedded Computing (MECO)10.1109/MECO.2018.8406051(1-6)Online publication date: Jun-2018
Ubar RKostin SJenihhin MRaik J(2017)A scalable technique to identify true critical paths in sequential circuits2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS.2017.7934568(152-157)Online publication date: Apr-2017
Matrosova AKudin DNikolaeva E(2014)Combinational circuits without false pathsProceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)10.1109/EWDTS.2014.7027103(1-6)Online publication date: Sep-2014
Wang (2007)System-on-Chip Test ArchitecturesundefinedOnline publication date: 20-Nov-2007
Ferrao DWilke GReis RNeves CAgostini LGuntzel J(2006)Safe Path-Based Hierarchical Functional Timing Analysis by Considering Block Arrival Times2006 International Caribbean Conference on Devices, Circuits and Systems10.1109/ICCDCS.2006.250885(345-349)Online publication date: Nov-2006
Bahar RCho HHachtel GMacii ESomenzi F(2006)Symbolic timing analysis and resynthesis for low power of combinational circuits containing false pathsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.66267416:10(1101-1115)Online publication date: 1-Nov-2006
Ferrão DReis RGüntzel J(2006)Considering zero-arrival time and block-arrival time in hierarchical functional timing analysisProceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11847083_29(301-310)Online publication date: 13-Sep-2006
Krishnamachary AAbraham J(2003)Effects of Multi-cycle Sensitization on Delay TestsProceedings of the 16th International Conference on VLSI Design10.5555/832285.835570Online publication date: 4-Jan-2003
Wangqi Qiu Walker D(2003)An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuitInternational Test Conference, 2003. Proceedings. ITC 2003.10.1109/TEST.2003.1270886(592-601)Online publication date: 2003
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