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View all- Raji MGhavami BRaji MGhavami B(2022)Joint Timing Yield and Lifetime Reliability Optimization of Integrated CircuitsLifetime Reliability-aware Design of Integrated Circuits10.1007/978-3-031-15345-7_5(65-83)Online publication date: 17-Nov-2022
- Ebrahimipour SGhavami BRaji M(2021)A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated CircuitsIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2020.29879469:2(759-773)Online publication date: 1-Apr-2021
- Ebrahimipour SGhavami BRaji M(2019)Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuitsIET Circuits, Devices & Systems10.1049/iet-cds.2018.561613:7(979-987)Online publication date: 22-Oct-2019
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