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Incremental criticality and yield gradients

Published: 10 March 2008 Publication History

Abstract

Criticality and yield gradients are two crucial diagnostic metrics obtained from Statistical Static Timing Analysis (SSTA). They provide valuable information to guide timing optimization and timing-driven physical synthesis. Existing work in the literature, however, computes both metrics in a non-incremental manner, i.e., after one or more changes are made in a previously-timed circuit, both metrics need to be recomputed from scratch, which is obviously undesirable for optimizing large circuits. The major contribution of this paper is to propose two novel techniques to compute both criticality and yield gradients efficiently and incrementally. In addition, while node and edge criticalities are addressed in the literature, this paper for the first time describes a technique to compute path criticalities. To further improve algorithmic efficiency, this paper also proposes a novel technique to update "chip slack" incrementally. Numerical results show our methods to be over two orders of magnitude faster than previous work.

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Cited By

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  • (2022)Joint Timing Yield and Lifetime Reliability Optimization of Integrated CircuitsLifetime Reliability-aware Design of Integrated Circuits10.1007/978-3-031-15345-7_5(65-83)Online publication date: 17-Nov-2022
  • (2021)A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated CircuitsIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2020.29879469:2(759-773)Online publication date: 1-Apr-2021
  • (2019)Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuitsIET Circuits, Devices & Systems10.1049/iet-cds.2018.561613:7(979-987)Online publication date: 22-Oct-2019
  • Show More Cited By

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          cover image ACM Conferences
          DATE '08: Proceedings of the conference on Design, automation and test in Europe
          March 2008
          1575 pages
          ISBN:9783981080131
          DOI:10.1145/1403375
          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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          Published: 10 March 2008

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          DATE '08: Design, Automation and Test in Europe
          March 10 - 14, 2008
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          Overall Acceptance Rate 518 of 1,794 submissions, 29%

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          Cited By

          View all
          • (2022)Joint Timing Yield and Lifetime Reliability Optimization of Integrated CircuitsLifetime Reliability-aware Design of Integrated Circuits10.1007/978-3-031-15345-7_5(65-83)Online publication date: 17-Nov-2022
          • (2021)A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated CircuitsIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2020.29879469:2(759-773)Online publication date: 1-Apr-2021
          • (2019)Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuitsIET Circuits, Devices & Systems10.1049/iet-cds.2018.561613:7(979-987)Online publication date: 22-Oct-2019
          • (2016)Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield GradientACM Transactions on Design Automation of Electronic Systems10.1145/289681921:4(1-27)Online publication date: 18-May-2016
          • (2015)An efficient algorithm for statistical timing yield optimizationProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744796(1-6)Online publication date: 7-Jun-2015
          • (2012)On the computation of criticality in statistical timing analysisProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429418(172-179)Online publication date: 5-Nov-2012
          • (2012)Reversible statistical max/min operationProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228554(1067-1073)Online publication date: 3-Jun-2012
          • (2011)Fast statistical timing analysis for circuits with post-silicon tunable clock buffersProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132354(111-117)Online publication date: 7-Nov-2011
          • (2011)Path criticality computation in parameterized statistical timing analysisProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950873(249-254)Online publication date: 25-Jan-2011
          • (2011)Testability driven statistical path selectionProceedings of the 48th Design Automation Conference10.1145/2024724.2024822(417-422)Online publication date: 5-Jun-2011
          • Show More Cited By

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