Nothing Special   »   [go: up one dir, main page]

skip to main content
10.1145/1403375.1403631acmconferencesArticle/Chapter ViewAbstractPublication PagesdateConference Proceedingsconference-collections
research-article

EPIC: ending piracy of integrated circuits

Published: 10 March 2008 Publication History

Abstract

As semiconductor manufacturing requires greater capital investments, the use of contract foundries has grown dramatically, increasing exposure to mask theft and unauthorized excess production. While only recently studied, IC piracy has now become a major challenge for the electronics and defense industries [6].
We propose a novel comprehensive technique to end piracy of integrated circuits (EPIC). It requires that every chip be activated with an external key, which can only be generated by the holder of IP rights, and cannot be duplicated. EPIC is based on (i) automatically-generated chip IDs, (ii) a novel combinational locking algorithm, and (iii) innovative use of public-key cryptography. Our evaluation suggests that the overhead of EPIC on circuit delay and power is negligible, and the standard flows for verification and test do not require change. In fact, major required components have already been integrated into several chips in production. We also use formal methods to evaluate combinational locking and computational attacks. A comprehensive protocol analysis concludes that EPIC is surprisingly resistant to various piracy attempts.

References

[1]
Y. Alkabani and F. Koushanfar. Active hardware metering for intellectual property protection and security. In USENIX Security, pp. 291--306, 2007.
[2]
Y. Alkabani, F. Koushanfar, and M. Potkonjak. Remote activation of ICs for piracy prevention and digital rights management. In IEEE/ACM ICCAD, pp. 674--677, 2007.
[3]
R. Anderson. Security Engineering: A guide to building dependable distributed systems. John Wiley and Sons, 2001.
[4]
F. Brglez and H. Fujiwara. A neutral netlist of 10 combinational circuits and a target translator in FORTRAN. In IEEE ISCAS, 1985.
[5]
P. Clarke. Fake NEC company found, says report. EE Times, May 4, 2006. http://www.eetimes.com/showArticle.jhtml?articleID=187200176
[6]
Defense Science Board (DSB) study on High Performance Microchip Supply. http://www.acq.osd.mil/dsb/reports/2005-02-HPMS_Report_Final.pdf
[7]
N. Ferguson and B. Schneier. Practical Cryptography. John Wiley and Sons, 2003.
[8]
G. D. Hachtel and F. Somenzi. Logic Synthesis and Verification Algorithms. Kluwer, 2000
[9]
F. Koushanfar, G. Qu, and M. Potkonjak. Intellectual property metering. In Inf. Hiding Workshop, pp. 81--95, 2001.
[10]
M. LaPedus, Qualcomm cracks top-10 in chip rankings. EE Times, August 23, 2007. http://www.eetimes.com/news/semi/showArticle.jhtml?articleID= 201801923
[11]
K. Lofstrom, W. Daasch, and D. Taylor. IC identification circuits using device mismatch. In ISSCC, pp. 372--373, 2000.
[12]
C. Mouli and W. Carriker. Future fab. IEEE Spectrum 44(3), pp. 38--43, March 2007. http://www.spectrum.ieee.org/mar07/4941
[13]
U. M. Nawathe et al. An 8-Core 64-thread 64b power-efficient SPARC SoC. In ISSCC, pp. 108--611, 2007. http://www.opensparc.net/opensparc-t2/index.html
[14]
B. Santo, Plans for next-gen chips imperiled. IEEE Spectrum 44(8), pp. 12--14, August 2007.http://www.spectrum.ieee.org/aug07/5394
[15]
Sciworx RSA Co-Processor. http://www.sci-worx.com/products/cryptography/rsa-co-processor.html
[16]
F. Somenzi, CUDD: CU decision diagram package. ver. 2.4.1, Univ. of Colorado at Boulder, 2004. http://vlsi.colorado.edu/~fabio/CUDD/
[17]
Y. Su, J. Holleman, and B. Otis. A 1.6J/bit stable chip ID generating circuit using process variations. In ISSCC, pp. 406--611, 2007.
[18]
G. E. Suh and S. Devadas. Physical unclonable functions for device authentication and secret key generation. In DAC, pp. 9--14, 2007.
[19]
C. Tokunaga, D. Blaauw and T. Mudge. True random number generator with a metastability-based quality control. In IEEE ISSCC, pp. 404--405, 2007.
[20]
S. Trimberger. Trusted design in FPGAs. DAC "07, pp. 5--8.
[21]
VSI Alliance - IP Protection Development Working Group. The value and management of intellectual assets. 2000. http://vsi.org/documents/datasheets/TOC_IPPWP210.pdf

Cited By

View all
  • (2024)SmartDED: A Blockchain- and Smart Contract-Based Digital Electronic Detonator Safety Supervision SystemFuture Internet10.3390/fi1605017116:5(171)Online publication date: 16-May-2024
  • (2024)Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEP2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546500(1-6)Online publication date: 25-Mar-2024
  • (2024)FCLock: harnessing functional non-combinational cycles in logic lockingIEICE Electronics Express10.1587/elex.21.2024021821:12(20240218-20240218)Online publication date: 25-Jun-2024
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
DATE '08: Proceedings of the conference on Design, automation and test in Europe
March 2008
1575 pages
ISBN:9783981080131
DOI:10.1145/1403375
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 March 2008

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Research-article

Conference

DATE '08
Sponsor:
  • EDAA
  • SIGDA
  • The Russian Academy of Sciences
DATE '08: Design, Automation and Test in Europe
March 10 - 14, 2008
Munich, Germany

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25
Design, Automation and Test in Europe
March 31 - April 2, 2025
Lyon , France

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)96
  • Downloads (Last 6 weeks)7
Reflects downloads up to 23 Nov 2024

Other Metrics

Citations

Cited By

View all
  • (2024)SmartDED: A Blockchain- and Smart Contract-Based Digital Electronic Detonator Safety Supervision SystemFuture Internet10.3390/fi1605017116:5(171)Online publication date: 16-May-2024
  • (2024)Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEP2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546500(1-6)Online publication date: 25-Mar-2024
  • (2024)FCLock: harnessing functional non-combinational cycles in logic lockingIEICE Electronics Express10.1587/elex.21.2024021821:12(20240218-20240218)Online publication date: 25-Jun-2024
  • (2024)Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of FunctionalityACM Transactions on Design Automation of Electronic Systems10.1145/367490329:4(1-23)Online publication date: 25-Jun-2024
  • (2024)SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented EstimationProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3660382(489-494)Online publication date: 12-Jun-2024
  • (2024)LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit TransformationsProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658805(588-591)Online publication date: 12-Jun-2024
  • (2024)NoBALL: A Novel BDD-based Attack against Logic Locking2024 IEEE International Test Conference in Asia (ITC-Asia)10.1109/ITC-Asia62534.2024.10661361(1-6)Online publication date: 18-Aug-2024
  • (2024)LIPSTICK: Corruptibility-Aware and Explainable Graph Neural Network-Based Oracle-Less Attack on Logic LockingProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473982(606-611)Online publication date: 22-Jan-2024
  • (2024)Logic Locking over TFHE for Securing User Data and Algorithms2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473831(600-605)Online publication date: 22-Jan-2024
  • (2024)Secure hardware IP of GLRT cascade using color interval graph based embedded fingerprint for ECG detectorScientific Reports10.1038/s41598-024-63533-714:1Online publication date: 10-Jun-2024
  • Show More Cited By

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media