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Partitioned register files for VLIWs: a preliminary analysis of tradeoffs

Authors:

Andrea Capitanio,

Nikil Dutt,

Alexandru NicolauAuthors Info & Claims

ACM SIGMICRO Newsletter, Volume 23, Issue 1-2

Pages 292 - 300

https://doi.org/10.1145/144965.145839

Published: 10 December 1992 Publication History

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References

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Cited By

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Shah NMeert WVerhelst M(2022)DPU-v2: Energy-efficient execution of irregular directed acyclic graphs2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00090(1288-1307)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00090
Naresh VGope DLipasti M(2017)The CUREACM Transactions on Embedded Computing Systems10.1145/312652716:5s(1-19)Online publication date: 27-Sep-2017
https://dl.acm.org/doi/10.1145/3126527
Wu CLu CLee J(2014)Register spilling via transformed interference equations for PAC DSP architectureConcurrency and Computation: Practice & Experience10.1002/cpe.305126:3(779-799)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1002/cpe.3051
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Index Terms

Partitioned register files for VLIWs: a preliminary analysis of tradeoffs
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific instruction set processors

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Distributed register file architectures divide registers into multiple sets, and it follows that the register files could be small. This can increase the frequency of spilling if register allocation encounters high register pressure, which will reduce ...

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Published: 10 December 1992

Published in SIGMICRO Volume 23, Issue 1-2

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Shah NMeert WVerhelst M(2022)DPU-v2: Energy-efficient execution of irregular directed acyclic graphs2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00090(1288-1307)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00090
Naresh VGope DLipasti M(2017)The CUREACM Transactions on Embedded Computing Systems10.1145/312652716:5s(1-19)Online publication date: 27-Sep-2017
https://dl.acm.org/doi/10.1145/3126527
Wu CLu CLee J(2014)Register spilling via transformed interference equations for PAC DSP architectureConcurrency and Computation: Practice & Experience10.1002/cpe.305126:3(779-799)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1002/cpe.3051
Porpodas VCintra MRabbah RRaghunathan A(2013)CAeSaRProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555738(1-10)Online publication date: 29-Sep-2013
https://dl.acm.org/doi/10.5555/2555729.2555738
Porpodas VCintra M(2013)LUCASACM SIGPLAN Notices10.1145/2499369.246556548:5(45-54)Online publication date: 20-Jun-2013
https://dl.acm.org/doi/10.1145/2499369.2465565
Porpodas VCintra MFranke BXue J(2013)LUCASProceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems10.1145/2491899.2465565(45-54)Online publication date: 20-Jun-2013
https://dl.acm.org/doi/10.1145/2491899.2465565
Porpodas VCintra MFranke BXue J(2013)LUCASProceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems10.1145/2465554.2465565(45-54)Online publication date: 20-Jun-2013
https://dl.acm.org/doi/10.1145/2465554.2465565
Xu YZhizhong TDeyuan GHu H(2011)Backtracking Optimized DDG Directed Scheduling Algorithm for Clustered VLIW ArchitecturesProceedings of the 2011 International Conference on Future Computer Sciences and Application10.1109/ICFCSA.2011.25(82-85)Online publication date: 18-Jun-2011
https://dl.acm.org/doi/10.1109/ICFCSA.2011.25
Latorre FMagklis GGonzález JChaparro PGonzález A(2011)CROBProceedings of the 2011 conference on Transactions on High-Performance Embedded Architectures and Compilers III - Volume 659010.1007/978-3-642-19448-1_7(115-134)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1007/978-3-642-19448-1_7
Govindarajan R(2010)Instruction SchedulingThe Compiler Design Handbook10.1201/9781420040579.ch17Online publication date: 7-Mar-2010
https://doi.org/10.1201/9781420040579.ch17
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Software register synchronization for super-scalar processors with partitioned register files

Power Estimation of Partitioned Register Files in a Clustered Architecture with Performance Evaluation

Achieving spilling-friendly register file assignment for highly distributed register files

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