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Generalized instruction selection using SSA-graphs

Published: 12 June 2008 Publication History

Abstract

Instruction selection is a well-studied compiler phase that translates the compiler's intermediate representation of programs to a sequence of target-dependent machine instructions optimizing for various compiler objectives (e.g. speed and space). Most existing instruction selection techniques are limited to the scope of a single statement or a basic block and cannot cope with irregular instruction sets that are frequently found in embedded systems.
We consider an optimal technique for instruction selection that uses Static Single Assignment (SSA) graphs as an intermediate representation of programs and employs the Partitioned Boolean Quadratic Problem (PBQP) for finding an optimal instruction selection. While existing approaches are limited to instruction patterns that can be expressed in a simple tree structure, we consider complex patterns producing multiple results at the same time including pre/post increment addressing modes, div-mod instructions, and SIMD extensions frequently found in embedded systems. Although both instruction selection on SSA-graphs and PBQP are known to be NP-complete, the problem can be solved efficiently - even for very large instances.
Our approach has been implemented in LLVM for an embedded ARMv5 architecture. Extensive experiments show speedups of up to 57% on typical DSP kernels and up to 10% on SPECINT 2000 and MiBench benchmarks. All of the test programs could be compiled within less than half a minute using a heuristic PBQP solver that solves 99.83% of all instances optimally.

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  • (2022)An efficient hardware supported and parallelization architecture for intelligent systems to overcome speculative overheadsInternational Journal of Intelligent Systems10.1002/int.2306237:12(11764-11790)Online publication date: 8-Sep-2022
  • (2021)Instruction Code SelectionSSA-based Compiler Design10.1007/978-3-030-80515-9_19(257-268)Online publication date: 12-Jun-2021
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    Published In

    cover image ACM Conferences
    LCTES '08: Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
    June 2008
    180 pages
    ISBN:9781605581040
    DOI:10.1145/1375657
    • cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 43, Issue 7
      LCTES '08
      July 2008
      167 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/1379023
      Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 12 June 2008

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    Author Tags

    1. code generation
    2. compiler
    3. instruction selection
    4. pbqp

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    Cited By

    View all
    • (2023)The algorithm and implementation of an extension to LLVM for solving the blocking between instruction sink and division-modulo combineConnection Science10.1080/09540091.2023.227321935:1Online publication date: 30-Oct-2023
    • (2022)An efficient hardware supported and parallelization architecture for intelligent systems to overcome speculative overheadsInternational Journal of Intelligent Systems10.1002/int.2306237:12(11764-11790)Online publication date: 8-Sep-2022
    • (2021)Instruction Code SelectionSSA-based Compiler Design10.1007/978-3-030-80515-9_19(257-268)Online publication date: 12-Jun-2021
    • (2021)Graphs and Gating FunctionsSSA-based Compiler Design10.1007/978-3-030-80515-9_14(185-199)Online publication date: 12-Jun-2021
    • (2018)Fast and flexible instruction selection with constraintsProceedings of the 27th International Conference on Compiler Construction10.1145/3178372.3179501(93-103)Online publication date: 24-Feb-2018
    • (2018)Synthesizing an instruction selection rule library from semantic specificationsProceedings of the 2018 International Symposium on Code Generation and Optimization10.1145/3168821(300-313)Online publication date: 24-Feb-2018
    • (2017)Complete and Practical Universal Instruction SelectionACM Transactions on Embedded Computing Systems10.1145/312652816:5s(1-18)Online publication date: 27-Sep-2017
    • (2013)Intermediate representations in imperative compilersACM Computing Surveys10.1145/2480741.248074345:3(1-27)Online publication date: 3-Jul-2013
    • (2013)Automatic generation of compiler backendsSoftware—Practice & Experience10.1002/spe.210643:2(207-240)Online publication date: 1-Feb-2013
    • (2012)Compiling for automatically generated instruction set extensionsProceedings of the Tenth International Symposium on Code Generation and Optimization10.1145/2259016.2259019(13-22)Online publication date: 31-Mar-2012
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