The good, the bad, and the statistical

Recently, statistical static timing analysis (SSTA) has been proposed as a technique for mitigating the effects of parametric process variations on typical design metrics like performance and power (through circuit optimization). In spite of significant advances in the algorithmic state-of-the-art, the applicability of SSTA to general purpose IC design continues to be a matter of debate at various forums across the semiconductor and EDA industry. This talk will present analyses, studies, and trends which will highlight the applicability of statistical techniques at different stages of microprocessor design: skew calculation, min-delay computation, leakage estimation, bin-split prediction, and, finally, timing analysis. The increasing role of test in handling the effects of process variation will also be discussed. A case will be made that while SSTA may have applicability in the design of some products, there is a need for significant variation-related innovation to enable continued scaling.