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LiB: a cell layout generator

Authors:

Yung-Ching Hsieh,

Yu-Chin HsuAuthors Info & Claims

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

Pages 474 - 479

https://doi.org/10.1145/123186.123343

Published: 03 January 1991 Publication History

Abstract

We present an automatic layout generation system, called LiB, for the library cells used in CMOS ASIC design. LiB takes a transistor-level circuit schematic in SPICE format and outputs a symbolic layout. Our layout style is similar to that proposed by Uehara and van Cleemput in [17]. We propose several heuristic algorithms to solve the transistor-clustering, -pairing, -chaining, -folding, the chain placement, the routing, and the net assignment problems, respectively. Experimental results are presented to show the capability of LiB.

References

[1]

Balms, D. G., and J. Allen, "SOLO: A Generator of Efficient Layouts From Optimized MOS Circuit Schematics," 25th ACM/IEEE Design Automation Conference, pp. 445-452, 1988.

Digital Library

[2]

Chela, C.Y.R., and C.Y. Hou, "A New Layout Optimization Methodology for CMOS Complex Gates," ICCAD- 88, pp. 368-371, November 1988.

[3]

Hashimoto, A., and S. Stevens, "Wire Routing by Optimizing Channel Assignment within Large Apertures," 8th Design Automation Workshop: 155-169, 1971.

Digital Library

[4]

Hedlund, Kye S., "Aesop: A Tool for Automated Transistor Sizing," 24th ACM/IEEE Design Automation Conference, pp. 114-120, 1987.

Digital Library

[5]

Heeb, H., and W. Fichtner, "GRAPES: A Module Generator Based on Graph Planarity," ICCAD-87, pp.428-431, 1987.

[6]

Hill D. D., "Sc2: A Hybrid Automatic Layout System" ICCAD-85, pp. 172-174, November 1985.

[7]

Hwang, C. Y., Y. C. Hsieh, Y-L. Lin, and Y. C. Hsu, "An Optimal Transistor-Chaining Algorithm for CMOS Cell Layout," ICCAD-89, pp. 344-347, November 1989.

[8]

Kemighan, B. W. and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," Bell Syst. Teeh. J., Vol. 49, pp. 291-307, Feb. 19/0.

[9]

Kim, J., and L McDermott,'q'ALlB: An I(2 Layout Design Assistant," proceedings of the AAAI Conference, pp. 197-201, Washington, DC., 1983.

[10]

Kollaritsch, P. W. and N. H. E. Weste, "TOPOIZ)GIZER: An Expert System Translator of Transistor Connectivity to Symbolic Cell Layout," IEEE Journal of Solid-State Circuits, Vol. 20, No. 3, pp. 799-804, June 1985.

[11]

Lin, Y-L., and D. D. Gajski, "LES: A Layout Expert Systern," IEEE Trans. on CAD, Vol. 7, No. 8, pp. 868-876, August 1988.

[12]

Lin, Y-L., Y-C. Hsu, and F-S. Tsai., "SILK: A Simulated Evolution Router," IEEE Trans. on CAD, Vol. 8, No 10, pp. 1108-1114, October 1989.

[13]

Maziasz, R. L. and J. P. Hayes, "Layout Optimization of CMOS Functional Cells," Proceedings of 24th ACM/IEEE Design Automation Conference, pp. 544-551, June 1987.

Digital Library

[14]

Nair, R., A. Brass, and J. Reif, "Linear Time Algorithms for Optimal CMOS Layout," in VLSI Algorithms mad Architecture: Proceedings of the International Workshop on Parallel Computing and VLSI, Amalfi, italy, pp. 327- 338, May 1984.

[15]

Shiraishi, Y., J. Sakemk M. Kutsuwada, A. Tsuldzoe, and T. Satoh, " A High Packing Density Module Generator for CMOS Logic Cells," 25th ACM/IEEE Design Automarion Conference, pp. 439-444, 1988.

Digital Library

[16]

Stauffer, A., and R. Nair, "Optimal CMOS Cell Transistor Placement: A Relaxation Approach," Digest of Papers, ICCAD-88, pp. 364-367, November 1988.

[17]

Uehara, T. and W. M. van Cleemput, "Optimal Layout of CMOS Functional Arrays," IEEE Trans. on Computers, Vol. C-30, No. 5, pp. 305-312, May 1981.

[18]

Wimmer, S., R. Y. Pinter and J. A. Feldman, "Optimal Chaining of CMOS Transistors in a Functional CelL" IEEE Trans. on Computer-Aided Design, Vol. CAD-6, No. 5, pp. 795-801, September 1987.

[19]

Chela, C. C., and S. L. Chow, 'The Layout Synthesizer: An Automatic Netlist-to-Layout System," 26th ACM/IEEE Design Automation Conference, pp. 232-238, June, 1989.

Digital Library

[20]

Ong, C. L., J. T. Li, and C. Y. Lo, "GENAC: An Automatic Cell Synthesis Tool," 26th ACM/IEEE Design Automation Conference, pp. 239-244, June, 1989.

Digital Library

Cited By

Chavez-Martinez EChavez-Martinez MGurrola-Navarro M(2012)Modified standard cell methodology for VLSI layout compaction2012 9th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)10.1109/ICEEE.2012.6421201(1-6)Online publication date: Sep-2012
https://doi.org/10.1109/ICEEE.2012.6421201
Ziesemer ALazzar C(2007)Transistor level automatic layout generator for non-complementary CMOS cells2007 IFIP International Conference on Very Large Scale Integration10.1109/VLSISOC.2007.4402483(116-121)Online publication date: Oct-2007
https://doi.org/10.1109/VLSISOC.2007.4402483
Kim JKang SYoffa EDe Micheli GRabaey J(1997)An efficient transistor folding algorithm for row-based CMOS layout designProceedings of the 34th annual Design Automation Conference10.1145/266021.266199(456-459)Online publication date: 13-Jun-1997
https://dl.acm.org/doi/10.1145/266021.266199
Show More Cited By

Index Terms

LiB: a cell layout generator
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Integrated circuits

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cover image ACM Conferences

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

January 1991

742 pages

ISBN:0897913639

DOI:10.1145/123186

Chairman:
Richard C. Smith

Copyright © 1991 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 03 January 1991

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DAC90: The 27th ACM/IEEE-CS Design Automation Conference

June 24 - 27, 1990

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DAC '90 Paper Acceptance Rate 125 of 427 submissions, 29%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Chavez-Martinez EChavez-Martinez MGurrola-Navarro M(2012)Modified standard cell methodology for VLSI layout compaction2012 9th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)10.1109/ICEEE.2012.6421201(1-6)Online publication date: Sep-2012
https://doi.org/10.1109/ICEEE.2012.6421201
Ziesemer ALazzar C(2007)Transistor level automatic layout generator for non-complementary CMOS cells2007 IFIP International Conference on Very Large Scale Integration10.1109/VLSISOC.2007.4402483(116-121)Online publication date: Oct-2007
https://doi.org/10.1109/VLSISOC.2007.4402483
Kim JKang SYoffa EDe Micheli GRabaey J(1997)An efficient transistor folding algorithm for row-based CMOS layout designProceedings of the 34th annual Design Automation Conference10.1145/266021.266199(456-459)Online publication date: 13-Jun-1997
https://dl.acm.org/doi/10.1145/266021.266199
Jaewon Kim Kang S(1997)An Efficient Transistor Folding Algorithm For Row-based Cmos Layout DesignProceedings of the 34th Design Automation Conference10.1109/DAC.1997.597191(456-459)Online publication date: 1997
https://doi.org/10.1109/DAC.1997.597191
Sadakane TNakao HTerai M(1995)A new hierarchical algorithm for transistor placement in CMOS macro cell designProceedings of the IEEE 1995 Custom Integrated Circuits Conference10.1109/CICC.1995.518224(461-464)Online publication date: 1995
https://doi.org/10.1109/CICC.1995.518224
Anton ODoerffer KMlynski D(1993)Automatic design of transparent standard cells with TRANSCAD II1993 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.1993.693033(1853-1856)Online publication date: 1993
https://doi.org/10.1109/ISCAS.1993.693033
Anton ODoerffer KMlynski D(1993)Automatic design of transparent standard cells with TRANSCAD II1993 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.1993.394108(1853-1856)Online publication date: 1993
https://doi.org/10.1109/ISCAS.1993.394108
Chen TLouderback DSunada G(1992)Optimization of the number of levels of hierarchy in large-scale hierarchical memory systems[Proceedings] 1992 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.1992.230578(2104-2107)Online publication date: 1992
https://doi.org/10.1109/ISCAS.1992.230578
Nakagaki TYamada SFukunaga K(1992)Fast optimal algorithm for the CMOS functional cell layout based on transistor reordering[Proceedings] 1992 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.1992.230575(2116-2119)Online publication date: 1992
https://doi.org/10.1109/ISCAS.1992.230575
Maziasz RHayes JNewton A(1991)Exact width and height minimization of CMOS cellsProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127717(487-493)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127717
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