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Soft-well digital circuit design

Published: 03 September 2007 Publication History

Abstract

In this paper we present a novel digital design technique called soft-well circuit design improving digital circuits in fine-pitch technology. Improved noise immunity, higher-speed and reduced static power leakage may be traded for somewhat increased silicon area. The importance of soft-well design may increase in future technology where leakage and noise immunity is expected to severely impact circuit performance.

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  1. Soft-well digital circuit design

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      cover image ACM Conferences
      SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems design
      September 2007
      382 pages
      ISBN:9781595938169
      DOI:10.1145/1284480
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      New York, NY, United States

      Publication History

      Published: 03 September 2007

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      Author Tags

      1. low power design
      2. reliability
      3. well biasing

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      SBCCI07
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      SBCCI07: 20th Symposium on Integrated Circuits and System Design
      September 3 - 6, 2007
      Copacabana, Rio de Janeiro

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      Overall Acceptance Rate 133 of 347 submissions, 38%

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