Article

Satisfying whitespace requirements in top-down placement

Authors:

Jarrod A. Roy,

David A. Papa,

Aaron N. Ng,

Igor L. MarkovAuthors Info & Claims

ISPD '06: Proceedings of the 2006 international symposium on Physical design

Pages 206 - 208

https://doi.org/10.1145/1123008.1123053

Published: 09 April 2006 Publication History

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Abstract

In this invited note we outline several algorithms and features appearing in Capo 10, free open-source software for congestion-driven standard cell placement, mixed-size placement and floorplanning. Capo scales on par with industry placers and has been successfully used with a broad range of netlists. It can also satisfy lower bounds on local whitespace, using several techniques for global, detail and macro placement.

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Cited By

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Hsu MKatta NLin HLin KTam KWang KChang Y(2014)Design and manufacturing process co-optimization in nano-technologyProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691480(574-581)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691480
Hsu MKatta NLin HLin KTam KWang K(2014)Design and manufacturing process co-optimization in nano-technology (Designer Track Paper)2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2014.7001408(574-581)Online publication date: Nov-2014
https://doi.org/10.1109/ICCAD.2014.7001408
Chou SHsu MChang YGroeneveld PSciuto DHassoun S(2012)Structure-aware placement for datapath-intensive circuit designsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228498(762-767)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228498
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Index Terms

Satisfying whitespace requirements in top-down placement
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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Published In

ISPD '06: Proceedings of the 2006 international symposium on Physical design

April 2006

232 pages

ISBN:1595932992

DOI:10.1145/1123008

General Chair:
Lou Scheffer
Cadence

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 09 April 2006

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ISPD06

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ISPD06: International Symposium on Physical Design 2006

April 9 - 12, 2006

California, San Jose, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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March 16 - 19, 2025

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Cited By

View all

Hsu MKatta NLin HLin KTam KWang KChang Y(2014)Design and manufacturing process co-optimization in nano-technologyProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691480(574-581)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691480
Hsu MKatta NLin HLin KTam KWang K(2014)Design and manufacturing process co-optimization in nano-technology (Designer Track Paper)2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2014.7001408(574-581)Online publication date: Nov-2014
https://doi.org/10.1109/ICCAD.2014.7001408
Chou SHsu MChang YGroeneveld PSciuto DHassoun S(2012)Structure-aware placement for datapath-intensive circuit designsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228498(762-767)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228498
Ahmed ULemieux GWilton S(2011)Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs)IEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.207684119:12(2195-2208)Online publication date: 1-Dec-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2076841
Babu BSwetha RDevi K(2011)Comparision of Hierarchial Mixed-Size Placement Algorithms for VLSI Physical Synthesis2011 International Conference on Communication Systems and Network Technologies10.1109/CSNT.2011.95(430-435)Online publication date: Jun-2011
https://doi.org/10.1109/CSNT.2011.95
Chen HChuang YChang YChang YNassif SRoychowdhury J(2008)Constraint graph-based macro placement for modern mixed-size circuit designsProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509512(218-223)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509512
Nam GSze CYildiz MPan DNam G(2008)The ISPD global routing benchmark suiteProceedings of the 2008 international symposium on Physical design10.1145/1353629.1353663(156-159)Online publication date: 13-Apr-2008
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Chen TCho MPan DChang YPan DNam G(2008)Metal-density driven placement for cmp variation and routabilityProceedings of the 2008 international symposium on Physical design10.1145/1353629.1353638(31-38)Online publication date: 13-Apr-2008
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Chen TYuh PChang YHuang FLiu T(2008)MP-TreesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.92776027:9(1621-1634)Online publication date: 1-Sep-2008
https://dl.acm.org/doi/10.1109/TCAD.2008.927760
Chen TJiang ZHsu TChen HChang Y(2008)NTUplace3IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.92306327:7(1228-1240)Online publication date: 1-Jul-2008
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