Article

Design of a high performance FFT processor based on FPGA

Authors:

Chu Chao,

Zhang Qin,

Xie Yingke,

Han ChengdeAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 920 - 923

https://doi.org/10.1145/1120725.1121070

Published: 18 January 2005 Publication History

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Abstract

The design method of a real-time FFT processor is presented. By optimizing algorithm of memory mapping and generation of twiddle factors, a radix-4 butterfly can be calculated in one clock cycle. An approach to adaptive overflow control is also introduced to avoid overflow without interrupting the computing pipeline. The design is implemented on a FPGA chip and achieves the operating frequency at 127 MHz. It can complete a complex 1024-point FFT within 10.1 μs.

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Cited By

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Sankaran AReddy MArunkumar KBhaskar M(2020)Design and Implementation of 1024 Point Pipelined Radix 4 FFT Processor on FPGA for Biomedical Signal Processing Applications2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)10.1109/iSES50453.2020.00012(1-6)Online publication date: Dec-2020
https://doi.org/10.1109/iSES50453.2020.00012
Verdoscia LSahebi AGiorgi R(2019)A Data-Flow Methodology for Accelerating FFT2019 8th Mediterranean Conference on Embedded Computing (MECO)10.1109/MECO.2019.8760044(1-4)Online publication date: Jun-2019
https://doi.org/10.1109/MECO.2019.8760044
Junjie PYouyi FXiaofeng ZShuai KXinyu W(2018)Implementation of DFT application on ternary optical computerOptics Communications10.1016/j.optcom.2017.10.033410(424-430)Online publication date: Mar-2018
https://doi.org/10.1016/j.optcom.2017.10.033
Show More Cited By

Design of a high performance FFT processor based on FPGA
1. Mathematics of computing
  1. Mathematical analysis
    1. Numerical analysis

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Information & Contributors

Information

Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 January 2005

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Conference

ASPDAC05

Sponsor:

SIGDA

ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Cited By

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Sankaran AReddy MArunkumar KBhaskar M(2020)Design and Implementation of 1024 Point Pipelined Radix 4 FFT Processor on FPGA for Biomedical Signal Processing Applications2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)10.1109/iSES50453.2020.00012(1-6)Online publication date: Dec-2020
https://doi.org/10.1109/iSES50453.2020.00012
Verdoscia LSahebi AGiorgi R(2019)A Data-Flow Methodology for Accelerating FFT2019 8th Mediterranean Conference on Embedded Computing (MECO)10.1109/MECO.2019.8760044(1-4)Online publication date: Jun-2019
https://doi.org/10.1109/MECO.2019.8760044
Junjie PYouyi FXiaofeng ZShuai KXinyu W(2018)Implementation of DFT application on ternary optical computerOptics Communications10.1016/j.optcom.2017.10.033410(424-430)Online publication date: Mar-2018
https://doi.org/10.1016/j.optcom.2017.10.033
Vujovic SDakovic MOrovic IStankovic S(2015)An architecture for hardware realization of compressive sensing Gradient algorithm2015 4th Mediterranean Conference on Embedded Computing (MECO)10.1109/MECO.2015.7181900(189-192)Online publication date: Jun-2015
https://doi.org/10.1109/MECO.2015.7181900
Santhosh LThomas A(2013)Implementation of radix 2 and radix 2² FFT algorithms on Spartan6 FPGA2013 Fourth International Conference on Computing, Communications and Networking Technologies (ICCCNT)10.1109/ICCCNT.2013.6726840(1-4)Online publication date: Jul-2013
https://doi.org/10.1109/ICCCNT.2013.6726840
Zhou SWang XJi JWang Y(2013)Design and implementation of a 1024-point high-speed FFT processor based on the FPGA2013 6th International Congress on Image and Signal Processing (CISP)10.1109/CISP.2013.6745222(1112-1116)Online publication date: Dec-2013
https://doi.org/10.1109/CISP.2013.6745222
Sun MTian LDai D(2012)Radix-8 FFT processor design based on FPGA2012 5th International Congress on Image and Signal Processing10.1109/CISP.2012.6469786(1453-1457)Online publication date: Oct-2012
https://doi.org/10.1109/CISP.2012.6469786
Gavros ALoomis HRoss A(2011)Reduced Precision Redundancy in a Radix-4 FFT implementation on a Field Programmable Gate ArrayProceedings of the 2011 IEEE Aerospace Conference10.1109/AERO.2011.5747459(1-15)Online publication date: 5-Mar-2011
https://dl.acm.org/doi/10.1109/AERO.2011.5747459
Derafshi ZFrounchi JTaghipour H(2010)A High Speed FPGA Implementation of a 1024-Point Complex FFT ProcessorProceedings of the 2010 Second International Conference on Computer and Network Technology10.1109/ICCNT.2010.12(312-315)Online publication date: 23-Apr-2010
https://dl.acm.org/doi/10.1109/ICCNT.2010.12
Fangming Liu Xiaozhong Pan (2010)Research on implementation of FFT based on FPGA2010 International Conference on Computer Application and System Modeling (ICCASM 2010)10.1109/ICCASM.2010.5620808(V7-152-V7-155)Online publication date: Oct-2010
https://doi.org/10.1109/ICCASM.2010.5620808
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