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Design and test of a scalable security processor

Authors:

Cheng-Wen WuAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 372 - 375

https://doi.org/10.1145/1120725.1120872

Published: 18 January 2005 Publication History

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Abstract

This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18μm CMOS technology. The core area is 3.899mm x 2.296mm (525K gates approximately) and the operating clock rate is 83MHz.

References

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C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, "A high-throughput lowcost AES processor", IEEE Communications Magazine, vol. 41, no. 12, pp. 86--91, Dec. 2003.

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[2]

C.-H Wang, C.-P Su, C.-T Huang, and C.-W. Wu, "A word-based rsa crypto-processor with enhanced pipeline performance", in Proc. 4th IEEE Asia-Pacific Conf. ASIC, Fukuoka, Japan, Aug. 2004 (to appear).

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Xiao CZhang LXie YLiu WLiu D(2018)Hardware/Software Adaptive Cryptographic Acceleration for Big Data ProcessingSecurity and Communication Networks10.1155/2018/76313422018Online publication date: 27-Aug-2018
https://dl.acm.org/doi/10.1155/2018/7631342
Chen PLin JChang T(2009)IEEE standard 1500 compatible delay test frameworkIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201398317:8(1152-1156)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TVLSI.2009.2013983
Hong JLi W(2008)A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular MultiplierProceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2008.72(483-486)Online publication date: 7-Apr-2008
https://dl.acm.org/doi/10.1109/ISVLSI.2008.72
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Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 18 January 2005

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ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Xiao CZhang LXie YLiu WLiu D(2018)Hardware/Software Adaptive Cryptographic Acceleration for Big Data ProcessingSecurity and Communication Networks10.1155/2018/76313422018Online publication date: 27-Aug-2018
https://dl.acm.org/doi/10.1155/2018/7631342
Chen PLin JChang T(2009)IEEE standard 1500 compatible delay test frameworkIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201398317:8(1152-1156)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TVLSI.2009.2013983
Hong JLi W(2008)A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular MultiplierProceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2008.72(483-486)Online publication date: 7-Apr-2008
https://dl.acm.org/doi/10.1109/ISVLSI.2008.72
Wang Haixin Bai Guoqiang Chen Hongyi (2008)ZodiacProceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2008.4580160(91-96)Online publication date: 2-Jul-2008
https://dl.acm.org/doi/10.1109/ASAP.2008.4580160
Wang CLo CLee MYeh JHuang CWu CHuang SSentovich E(2006)A network security processor design based on an integrated SOC design and test platformProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147039(490-495)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1147039
Chen-Hsing Wang Chih-Yen Lo Min-Shenq Lee Jen-Chieh Yeh Chih-Tsun Huang Cheng-Wen Wu Shi-Yu Huang (2006)A network security processor design based on an integrated SOC design and test platform2006 43rd ACM/IEEE Design Automation Conference10.1109/DAC.2006.229266(490-495)Online publication date: 2006
https://doi.org/10.1109/DAC.2006.229266

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A network security processor design based on an integrated SOC design and test platform

Embedded SoPC Design with Nios II Processor and Verilog Examples

Design and implementation of a private and public key crypto processor and its application to a security system

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