Cited By
View all- Okada KUezono TMasu K(2006)Estimation of power reduction by on-chip transmission line for 45nm technologyProceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11847083_18(181-190)Online publication date: 13-Sep-2006
- Flynn MKang J(2005)Global signaling over lossy transmission linesProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129740(985-992)Online publication date: 31-May-2005
- Uezono TInoue JKyogoku TOkada KMasu KMarkov IHutton M(2005)Prediction of delay time for future LSI using on-chip transmission line interconnectsProceedings of the 2005 international workshop on System level interconnect prediction10.1145/1053355.1053359(7-12)Online publication date: 2-Apr-2005