Article

Design and implementation of transducer for ARM-TMS communication

Authors:

Hansu Cho,

Samar Abdi,

Daniel GajskiAuthors Info & Claims

ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Pages 126 - 127

https://doi.org/10.1145/1118299.1118339

Published: 24 January 2006 Publication History

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Abstract

Communication between components, with different interface protocols, requires an extra component that must translate one protocol to another. This component is referred to as a transducer. In this paper we describe the design and implementation of a transducer between AMBA bus and TMS DSP bus. The transducer allows system designers to send data from AMBA compliant components to TMS compliant ones, and vice versa. The transducer was modeled in Verilog and implemented on Xilinx VirtexII FPGA board.

References

[1]

ARM Inc. ARM1020T Manual. Available http://www.arm.com/pdfs/DDI0135A_1020T.

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[2]

Texas Instruments Inc. TMS32C5x User's Guide. Avaiable http://focus.ti.com/.

Google Scholar

[3]

Xilinx Inc. DS031-Virtex-II Platform FPGAs: Complete Data Sheet. Available http://direct.xilinx.com/bvdocs/publications/ds031.pdf.

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Cited By

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Pasricha SDutt N(2008)On-Chip Communication Architecture Refinement and Interface SynthesisOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00009-8(341-366)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00009-8
Bombieri NFummi FPravadelli GLauwereins RMadsen J(2007)Incremental ABV for functional validation of TL-to-RTL design refinementProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266557(882-887)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266557
Bombieri NFummi FPravadelli GFedeli A(2007)Hybrid, Incremental Assertion-Based Verification for TLM Design FlowsIEEE Design & Test10.1109/MDT.2007.4824:2(140-152)Online publication date: 1-Mar-2007
https://dl.acm.org/doi/10.1109/MDT.2007.48
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Index Terms

Design and implementation of transducer for ARM-TMS communication
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Interconnect
    2. Logic circuits

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Information

Published In

ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

January 2006

998 pages

ISBN:0780394518

General Chair:
Fumiyasu Hirose
Cadence Design Systems, Japan

Publisher

IEEE Press

Publication History

Published: 24 January 2006

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Pasricha SDutt N(2008)On-Chip Communication Architecture Refinement and Interface SynthesisOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00009-8(341-366)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00009-8
Bombieri NFummi FPravadelli GLauwereins RMadsen J(2007)Incremental ABV for functional validation of TL-to-RTL design refinementProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266557(882-887)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266557
Bombieri NFummi FPravadelli GFedeli A(2007)Hybrid, Incremental Assertion-Based Verification for TLM Design FlowsIEEE Design & Test10.1109/MDT.2007.4824:2(140-152)Online publication date: 1-Mar-2007
https://dl.acm.org/doi/10.1109/MDT.2007.48
Bombieri NFummi FPravadelli G(2007)Incremental ABV for Functional Validation of TL-to-RTL Design Refinement2007 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2007.364404(1-6)Online publication date: Apr-2007
https://doi.org/10.1109/DATE.2007.364404
Gorjiara BReshadi MChandraiah PGajski DBergamaschi RChoi K(2006)Generic netlist representation for system and PE level design explorationProceedings of the 4th international conference on Hardware/software codesign and system synthesis10.1145/1176254.1176323(282-287)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176254.1176323

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ARM Synthesizable Design with Actel FPGAs: with Mixed-Signal SoC Applications (set 3)

Design and implementation of real time secured RS232 link for multiple FPGA communication

Regular Transducer Expressions for Regular Transformations

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