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Power optimization in a repeater-inserted interconnect via geometric programming

Published: 04 October 2006 Publication History

Abstract

We present an innovative geometric programming (GP) approach for minimizing the power dissipation of an interconnect with repeater insertion, subject to delay, bandwidth and area constraints. Repeater sizes and segment lengths are globally optimized in various technology nodes with respect to International Technology Roadmap for Semiconductors (ITRS). Relative power dissipation due to different power components is analyzed. We show that, on average, the power dissipation per unit length can be reduced by over 30% when the timing constraint is relaxed by 5%. The optimum number of repeaters is always given as an integer in our design flow. The relationships between power dissipation and respective design constraints are easily visualized in tradeoff curves. Additional design criteria, such as reliability of the interconnect delay against process variations, are easily incorporated into the optimization.

References

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      cover image ACM Conferences
      ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design
      October 2006
      446 pages
      ISBN:1595934626
      DOI:10.1145/1165573
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 04 October 2006

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      Author Tags

      1. geometric programming
      2. interconnect
      3. optimization
      4. power
      5. repeater

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      ISLPED06
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      ISLPED06: International Symposium on Low Power Electronics and Design
      October 4 - 6, 2006
      Bavaria, Tegernsee, Germany

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