Article

Optimality study of resource binding with multi-Vdds

Authors:

Junjuan XuAuthors Info & Claims

DAC '06: Proceedings of the 43rd annual Design Automation Conference

Pages 580 - 585

https://doi.org/10.1145/1146909.1147059

Published: 24 July 2006 Publication History

Abstract

Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource binding targeting designs with multi-Vdds. This is similar to the voltage-island design concept, except that the granularity of our voltage island is on the functional-unit level as opposed to the core level. We are interested in achieving the maximum number of low-Vdd operations and, in the same time, minimizing switching activity during functional unit binding. To the best of our knowledge, there is no known optimal solution to this problem. To compute an optimal solution for this problem and examine the quality gap between our solution and previous heuristic solutions, we formulate this problem as a min-cost network flow problem, but with special equal-flow constraints. This formulation leads to an easy reduction to the integer linear programming (ILP) solution and also enables efficient approximate solution by Lagrangian relaxation. Experimental results show that the optimal solution computed based on our formulation provides 7% more low-Vdd operations and also reduces the total switching activity by 20% compared to one of the best known heuristic algorithms that consider multi-Vdd assignments only.

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Cited By

Kim CJeong SCho SLee YSong WKim YKim HLee J(2021)Thread-aware area-efficient high-level synthesis compiler for embedded devicesProceedings of the 2021 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO51591.2021.9370341(327-339)Online publication date: 27-Feb-2021
https://dl.acm.org/doi/10.1109/CGO51591.2021.9370341
Hao CWang NYoshimura T(2017)A Unified Scheduling Approach for Power and Resource Optimization With Multiple $V_{\mathrm{ dd}}$ or/and $V_{\mathrm{ th}}$ in High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.266183036:12(2030-2043)Online publication date: Dec-2017
https://doi.org/10.1109/TCAD.2017.2661830
Zhang ZChen DDai SCampbell K(2015)High-level Synthesis for Low-power DesignIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.8.128(12-25)Online publication date: 2015
https://doi.org/10.2197/ipsjtsldm.8.12
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Optimality study of resource binding with multi-Vdds

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Published In

cover image ACM Conferences

DAC '06: Proceedings of the 43rd annual Design Automation Conference

July 2006

1166 pages

ISBN:1595933816

DOI:10.1145/1146909

General Chair:
Ellen M. Sentovich
Cadence Berkeley Labs, Berkeley, CA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 24 July 2006

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July 24 - 28, 2006

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Cited By

Kim CJeong SCho SLee YSong WKim YKim HLee J(2021)Thread-aware area-efficient high-level synthesis compiler for embedded devicesProceedings of the 2021 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO51591.2021.9370341(327-339)Online publication date: 27-Feb-2021
https://dl.acm.org/doi/10.1109/CGO51591.2021.9370341
Hao CWang NYoshimura T(2017)A Unified Scheduling Approach for Power and Resource Optimization With Multiple $V_{\mathrm{ dd}}$ or/and $V_{\mathrm{ th}}$ in High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.266183036:12(2030-2043)Online publication date: Dec-2017
https://doi.org/10.1109/TCAD.2017.2661830
Zhang ZChen DDai SCampbell K(2015)High-level Synthesis for Low-power DesignIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.8.128(12-25)Online publication date: 2015
https://doi.org/10.2197/ipsjtsldm.8.12
Li PZhang PPouchet LCong JConstantinides GChen D(2015)Resource-Aware Throughput Optimization for High-Level SynthesisProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689065(200-209)Online publication date: 22-Feb-2015
https://dl.acm.org/doi/10.1145/2684746.2689065
ITO K(2014)Energy Minimization of Full TMR Design with Optimized Selection of Temporal/Spatial TMR Mode and Supply VoltageIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E97.A.2530E97.A:12(2530-2539)Online publication date: 2014
https://doi.org/10.1587/transfun.E97.A.2530
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Demiriz ABagherzadeh NOzturk O(2014)Voltage island based heterogeneous NoC design through constraint programmingComputers and Electrical Engineering10.1016/j.compeleceng.2014.08.00540:8(307-316)Online publication date: 1-Nov-2014
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Kondratyev ALavagno LMeyer MWatanabe YMacii E(2013)Share with careProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485657(1547-1552)Online publication date: 18-Mar-2013
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Hadjis SCanis AAnderson JChoi JNam KBrown SCzajkowski TCompton KHutchings B(2012)Impact of FPGA architecture on resource sharing in high-level synthesisProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145712(111-114)Online publication date: 22-Feb-2012
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Alvarado UBistué GAdín IAlvarado UBistué GAdín I(2011)Schematic Design Techniques for Power Saving in RFLow Power RF Circuit Design in Standard CMOS Technology10.1007/978-3-642-22987-9_5(61-85)Online publication date: 2011
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