Article

Practical aspects of reliability analysis for IC designs

Authors:

J. SchneiderAuthors Info & Claims

DAC '06: Proceedings of the 43rd annual Design Automation Conference

Pages 193 - 198

https://doi.org/10.1145/1146909.1146962

Published: 24 July 2006 Publication History

Abstract

Voltage analysis is a major part of design-in reliability as voltage is the driver for electric degradation in dielectrics and MOS devices. Particularly, voltage has the largest influence on gate oxide reliability. An important trend designers should be aware of is the planned shift to new gate oxide failure criteria, which will tolerate progressive soft breakdowns in the gate oxide introducing additional gate leakage and noise. With increasing electric oxide fields negative bias instability of pFET devices became a severe problem, which cannot be solved by technology alone but requires also design solutions. Thus, simulation of MOSFETs being degraded by hot carrier stress and negative bias temperature stress becomes mandatory, as well as the control of device properties of circuit elements in a design. Design-in reliability in the metallization levels mainly is related to via placing and therefore, design tools should be able to trade off between increase in size, e.g. due to redundant vias, and benefit in reliability. Analysis of metal lines with maximum potential difference and minimal spacing also becomes mandatory in order to calculate the risk of time-dependent dielectric breakdown in the inter-metal dielectric, particularly for low-k dielectrics. From ESD point of view the following demands exist for future EDA solutions: 1) verification of net oriented ESD rules, 2) IR-drop analysis on layout to check ESD metallization rules, and 3) automatic placement of ESD or I/O cells depending on some formalized ESD guide lines that codify the ESD protection concept.

References

[1]

A. Amerasekera, C. Duvvury, "ESD in Silicon Integrated Circuit's", 2nd Ed., John Wiley & Sons, Ltd., 2002

[2]

Cadence Design Systems, Inc., "Reliability Simulation in Integrated Circuit Design", http://www.cadence.com/whitepapers

[3]

S Chakravarthi et al., Proc. Int. Reliab. Phys. Symp., pp. 273--282, 2004

[4]

C. Cheung, "Process Induced Damage in Advanced CMOS", tutorial at Int. Reliability Phys. Symp., 2005

[5]

J. Chung et al., Tech. Digest IEDM, pp. 553--556, 1990

[6]

T. Hook, "Process induced damage - a history and prognosis", tutorial at Int. Reliability Phys. Symp., 2006

[7]

C. Hu et al., IEEE Trans. on Electr. Dev., 32(2), pp. 375--385, 1985

[8]

Int. Tech. Roadmap for Semiconductors (ITRS), 2005

[9]

K.O. Jeppson et al., J. Appl. Phys., 48(5), pp. 2004--2014, 1977

[10]

A. Kerber et al., accepted for publ. in IEEE Electr. Dev. Letters, 2006

[11]

G. La Rosa et al., Proc. Int. Reliability Phys. Symp., pp. 282--286, 1997

[12]

B. Li et al., Proc. Int. Reliability Phys. Symp., pp. 24--30, 2005

[13]

Y.K. Lim et al., Proc. Int. Reliability Phys. Symp., pp. 203--208, 2005

[14]

M. H. Lin et al., Proc. Int. Reliability Phys. Symp., pp. 229--233, 2004

[15]

E. Miranda et al., IEEE Electr. Dev. Letters, 20(6), pp. 265--267, 1999

[16]

F. Monsieur et al., Proc. Int. Reliability Phys. Symp., pp. 45--54, 2002

[17]

D. Ney et al., Proc. Int. Reliability Phys. Symp., pp. 669--670, 2006

[18]

E.T. Ogawa et al., Proc. Int. Reliab. Phys. Symp., pp. 312--321, 2003

[19]

H. Reisinger et al., Proc. Int. Reliab. Phys. Symp., pp. 448--453, 2006

[20]

M. Röhner et al., Proc. Int. Reliability Phys. Symp., pp. 76--81, 2006

[21]

P.J. Roussel et al., IEEE Trans. on Device and Materials Reliability, 1(2), pp. 120--127, 2001

[22]

C. Schlünder et al., Microelectronics Reliability, 39 (Proc. ESREF), pp. 821--826, 1999

[23]

C. Schlünder et al., Proc. Int. Reliability Phys. Symp., pp. 5--10, 2003

[24]

C. Schlünder, "Mixed Signal Circuit Reliability", tutorial at Int. Reliability Phys. Symp., 2005

[25]

C. Schlünder, "Mixed Signal Circuit Reliability", tutorial at Proc. Int. Reliability Phys. Symp., 2006

[26]

R. Thewes et al, Proc. Int. Reliability Phys. Symp., pp. 233--238, 1999

[27]

R. Thewes et al., European Solid-State Device Research Conf. (ESSDERC), pp. 73--80, 2001

[28]

A. v. Glasow et al., Proc. Adv. Metallizat. Conf., pp. 161--167, 2002

[29]

A. v. Glasow et al., Proc. of Adv. Metallizat. Conf., pp. 433--440, 2001

[30]

A.Z.H. Wang, "On-Chip ESD Protection for Integrated Circuits. An IC Design Perspective", Kluwer Academic Publishers, 2002 might be damaged during an ESD event.

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Seo YRoy K(2018)High-Density SOT-MRAM Based on Shared Bitline StructureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.282284126:8(1600-1603)Online publication date: Aug-2018
https://doi.org/10.1109/TVLSI.2018.2822841
Seo YKwon KFong XRoy K(2016)High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAMIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2016.25477016:3(293-304)Online publication date: Sep-2016
https://doi.org/10.1109/JETCAS.2016.2547701
Bashir MChen CMilor LKim DLim S(2014)Backend Dielectric Reliability Full Chip SimulatorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.227785622:8(1750-1762)Online publication date: Aug-2014
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Index Terms

Practical aspects of reliability analysis for IC designs
1. Hardware
  1. Robustness

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cover image ACM Conferences

DAC '06: Proceedings of the 43rd annual Design Automation Conference

July 2006

1166 pages

ISBN:1595933816

DOI:10.1145/1146909

General Chair:
Ellen M. Sentovich
Cadence Berkeley Labs, Berkeley, CA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 24 July 2006

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Cited By

Seo YRoy K(2018)High-Density SOT-MRAM Based on Shared Bitline StructureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.282284126:8(1600-1603)Online publication date: Aug-2018
https://doi.org/10.1109/TVLSI.2018.2822841
Seo YKwon KFong XRoy K(2016)High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAMIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2016.25477016:3(293-304)Online publication date: Sep-2016
https://doi.org/10.1109/JETCAS.2016.2547701
Bashir MChen CMilor LKim DLim S(2014)Backend Dielectric Reliability Full Chip SimulatorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.227785622:8(1750-1762)Online publication date: Aug-2014
https://doi.org/10.1109/TVLSI.2013.2277856
Chen CBashir MMilor LKim DLim S(2012)Backend dielectric chip reliability simulator for complex interconnect geometries2012 IEEE International Reliability Physics Symposium (IRPS)10.1109/IRPS.2012.6241878(BD.4.1-BD.4.8)Online publication date: Apr-2012
https://doi.org/10.1109/IRPS.2012.6241878
Chen CAhmed FKim DLim SMilor L(2012)Backend dielectric reliability simulator for microprocessor systemMicroelectronics Reliability10.1016/j.microrel.2012.07.00252:9-10(1953-1959)Online publication date: Sep-2012
https://doi.org/10.1016/j.microrel.2012.07.002
Scheit DVierhaus H(2011)Self-Repair Technology for Global Interconnects on SoCsDesign and Test Technology for Dependable Systems-on-Chip10.4018/978-1-60960-212-3.ch009(195-215)Online publication date: 2011
https://doi.org/10.4018/978-1-60960-212-3.ch009
Bashir MMilor LKim DLim S(2011)Impact of irregular geometries on low-k dielectric breakdownMicroelectronics Reliability10.1016/j.microrel.2011.07.00551:9-11(1582-1586)Online publication date: Sep-2011
https://doi.org/10.1016/j.microrel.2011.07.005
Pey KRaghavan NWu XLiu WLi XBosman MShubhakar KLwin ZChen YQin HKauerauf T(2011)Physical analysis of breakdown in high-κ/metal gate stacks using TEM/EELS and STM for reliability enhancement (invited)Microelectronic Engineering10.1016/j.mee.2011.03.01288:7(1365-1372)Online publication date: Jul-2011
https://doi.org/10.1016/j.mee.2011.03.012
Bâzu MBăjenescu T(2011)Failure Analysis – What?Failure Analysis10.1002/9781119990093.ch5(109-246)Online publication date: 26-Apr-2011
https://doi.org/10.1002/9781119990093.ch5
Schlünder C(2009)Device reliability challenges for modern semiconductor circuit design – a reviewAdvances in Radio Science10.5194/ars-7-201-20097(201-211)Online publication date: 19-May-2009
https://doi.org/10.5194/ars-7-201-2009
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