Technology and architecture for deep submicron RF CMOS technology

RF CMOS is becoming a competitor for the technology of choice for large volume (RFID, WLAN), low and moderate RF frequency range applications (0.9 - 10 GHz). This conclusion would also hold for 65nm node, however it is expected that for the 45nm CMOS devices might differ significantly from 90nm and 65nm bulk CMOS because of the introduction of advanced process modules (like fully silicided gates, metal gates, high-k dielectrics, high mobility layers, ...) and new architecture (fully depleted SOI finfet). From the SOC design point of view, the increased digital device performance might be limited by analog performance limits and supply voltage reduction. In this contribution we present results for 90nm RFCMOS technology including active and passive components and various circuit demonstrator. The importance of passive components is illustrated with a VCO and LNA showing record performances with very low power consumption. The impact of further scaling is also presented to illustrate the trends and the limits for analog and RF performances.