Making router buffers much smaller

Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power ...

Network-on-chip (NoC) architectures are fast becoming an attractive solution to address the interconnect delay problems in chip multiprocessors (CMPs). However, increased power dissipation and limited performance improvements have hindered the wide-...

Microarchitectural configurations of buffers in routers have a significant impact on the overall performance of an on-chip network (NoC). This buffering can be at the inputs or the outputs of a router, corresponding to an input-buffered router (IBR) or ...