Article

Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry

Authors:

M. Y. Lanzerotti,

R. A. RandAuthors Info & Claims

SLIP '05: Proceedings of the 2005 international workshop on System level interconnect prediction

Pages 43 - 50

https://doi.org/10.1145/1053355.1053366

Published: 02 April 2005 Publication History

Abstract

This paper presents a comprehensive assessment of interconnect requirements in ULSI control logic circuitry and quantifies the agreement observed (1) between estimates and measurements of average wire-length in individual designs in real chips, and (2) between wire-length distributions provided by the models and wire-length distributions obtained from measurements. In this study, actual interconnect data is measured in ASIC-like control logic designs in the six functional units of the 1.3GHz POWER4. This paper compares interconnect measurements with estimates for control logic in individual designs, in functional units, and in the entire POWER4 core. The results presented in this paper show that the estimates are typically lower than the actual wire-length measurements. The results also show that the estimates of the total wire-length for all of the control logic in the POWER4 agree to within 31% of the total measured wire-length.

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Cited By

Beiu VMadappuram BKelly PMcDaid L(2011)On two-layer brain-inspired hierarchical topologies – a rent's rule approach –Transactions on High-Performance Embedded Architectures and Compilers IV10.5555/2172445.2172465(311-333)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.5555/2172445.2172465
Nain RChrzanowska-Jeske M(2011)Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence PairsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.205524719:9(1667-1680)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2055247
Beiu VMadappuram BKelly PMcDaid L(2011)On Two-Layer Brain-Inspired Hierarchical Topologies – A Rent’s Rule Approach –Transactions on High-Performance Embedded Architectures and Compilers IV10.1007/978-3-642-24568-8_16(311-333)Online publication date: 2011
https://doi.org/10.1007/978-3-642-24568-8_16
Show More Cited By

Index Terms

Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Published In

cover image ACM Conferences

SLIP '05: Proceedings of the 2005 international workshop on System level interconnect prediction

April 2005

114 pages

ISBN:1595930337

DOI:10.1145/1053355

General Chair:
Igor Markov
University of Michigan, USA
,
Program Chair:
Mike Hutton
Altera, USA

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 02 April 2005

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SLIP05: International Workshop on System Level Interconnect Prediction

April 2 - 3, 2005

California, San Francisco, USA

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Cited By

Beiu VMadappuram BKelly PMcDaid L(2011)On two-layer brain-inspired hierarchical topologies – a rent's rule approach –Transactions on High-Performance Embedded Architectures and Compilers IV10.5555/2172445.2172465(311-333)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.5555/2172445.2172465
Nain RChrzanowska-Jeske M(2011)Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence PairsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.205524719:9(1667-1680)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2055247
Beiu VMadappuram BKelly PMcDaid L(2011)On Two-Layer Brain-Inspired Hierarchical Topologies – A Rent’s Rule Approach –Transactions on High-Performance Embedded Architectures and Compilers IV10.1007/978-3-642-24568-8_16(311-333)Online publication date: 2011
https://doi.org/10.1007/978-3-642-24568-8_16
Madappuram BBeiu VKelly PMcDaid L(2008)On brain-inspired connectivity and hybrid network topologiesProceedings of the 2008 IEEE International Symposium on Nanoscale Architectures10.1109/NANOARCH.2008.4585792(54-61)Online publication date: 12-Jun-2008
https://dl.acm.org/doi/10.1109/NANOARCH.2008.4585792
Beiu VIbrahim W(2008)Does the brain really outperform Rent’s rule?2008 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2008.4541499(640-643)Online publication date: May-2008
https://doi.org/10.1109/ISCAS.2008.4541499
Beiu VMadappuram BMcGinnity M(2008)On brain-inspired hybrid topologies for nano-architectures - a Rent’s rule approach -2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1109/ICSAMOS.2008.4664844(33-40)Online publication date: Jul-2008
https://doi.org/10.1109/ICSAMOS.2008.4664844
Lanzerotti MFiorenza GRand RKennings AMandoiu I(2007)Impact of interconnect length changes on effective materials properties (dielectric constant)Proceedings of the 2007 international workshop on System level interconnect prediction10.1145/1231956.1231972(73-80)Online publication date: 17-Mar-2007
https://dl.acm.org/doi/10.1145/1231956.1231972
Amakawa SUezono TSato TOkada KMasu KKennings AMandoiu I(2007)Adaptable wire-length distribution with tunable occupation probabilityProceedings of the 2007 international workshop on System level interconnect prediction10.1145/1231956.1231958(1-8)Online publication date: 17-Mar-2007
https://dl.acm.org/doi/10.1145/1231956.1231958

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