Article

VPart: an automatic partitioning tool for dynamic reconfiguration (abstract only)

Authors:

Leos Kafka,

Rafal Kielbik,

Rudolf Matousek,

Juan Manuel MorenoAuthors Info & Claims

FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

Page 263

https://doi.org/10.1145/1046192.1046230

Published: 20 February 2005 Publication History

Get Access

Abstract

This paper presents an innovative tool for automatic partitioning of VHDL designs for dynamic reconfiguration called VPart. An introduction to the dynamic implementation of a circuit is presented. A design flow and optimization algorithms and methods used by the tool to partition the input design are explained. The usage of the tool is shown on three simple experiments performed on 18-bit floating-point arithmetic adder and multiplier.

Recommendations

Optimized reversible binary-coded decimal adders

Babu and Chowdhury [H.M.H. Babu, A.R. Chowdhury, Design of a compact reversible binary coded decimal adder circuit, Journal of Systems Architecture 52 (5) (2006) 272-282] recently proposed, in this journal, a reversible adder for binary-coded decimals. ...
Hardware Designs for Decimal Floating-Point Addition and Related Operations

Decimal arithmetic is often used in commercial, financial, and Internet-based applications. Due to the growing importance of decimal floating-point (DFP) arithmetic, the IEEE 754 Draft Standard for Floating-Point Arithmetic (IEEE P754) includes ...
Logic Networks of Carry-Save Adders

logic networks of carry-save adders such as high-speed multipliers, multioperand adders, and double-rail input parallel adders are designed based on the parallel adders with a minimum number of NOR gates discussed in [1]. After a discussion of the ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

February 2005

288 pages

ISBN:1595930299

DOI:10.1145/1046192

General Chair:
Herman Schmit
Tabula
,
Program Chair:
Steve Wilton
University of British Columbia

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 20 February 2005

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

FPGA05

Sponsor:

FPGA05: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2005

February 20 - 22, 2005

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

0
Total Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 18 Nov 2024

Other Metrics

View Author Metrics

Citations

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Recommendations

Optimized reversible binary-coded decimal adders

Hardware Designs for Decimal Floating-Point Addition and Related Operations

Logic Networks of Carry-Save Adders