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Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications

Authors:

Stefaan Note,

Werner Geurts,

Francky Catthoor,

Hugo De ManAuthors Info & Claims

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

Pages 597 - 602

https://doi.org/10.1145/127601.127739

Published: 01 June 1991 Publication History

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References

[1]

H. De Man, J. Kabaey, P. Six, L. Claesen, "CATHEDRAL-II : A Silicon compiler for Digital Signal Processing", IEEE Design and Test, Dec, 1986.

Google Scholar

[2]

B. Haroun, M. Elmasry, "SPAID : An Architectural Synthesis Tool for DSP Custom Applications", IEEE J. of Solid State Circuits, Vol 24, No.2, April, 1989.

Crossref

Google Scholar

[3]

S. Devadas and A. R. Newton "Algorithms for Hardware Allocation in Data Path Synthesis", IEEE Transactions on the Computer Aided Design of integrated Circuits and Systems, pp. 768-781, Vol.8 No.7, July 1989.

Google Scholar

[4]

N. Park, A. Parker, "Sehwa: A Software Package for Synthesis of Pipelines from Behavioural Specifications", {EEE Transactions on Computer Aided Design, Vol. 7, No. 3, March, 1988.

Google Scholar

[5]

N. Park, F. J. Kurdahi "Module Assignment and Interconnect Sharing in Register-Transfer Synthesis of Pipelined Data Paths" Proc. IEEE International Con- .ference on Computer Aided Design, pp. 16-19, Santa Clara, Calif., Nov. 1989.

Google Scholar

[6]

K.S. Hwang, A.E. Casavant, C.Chang, M.A. d'Abreu, "Scheduling and Hardware Sharing in Pipelined Datapaths", IEEE international Conference on Computer- Aided Design, Santa Clara, California, Nov. 1989.

Google Scholar

[7]

C. Chu, M. Potkonjak, M. Thaler, J. Kabaey, "HY- PER :An interactive Synthesis Environment for High Performance Real Time Applications", IEEE Intern. Conference on Computer Design, Cambridge, 1989.

Google Scholar

[8]

F.Catthoor, H.De Man, "Application-specific architectural methodologies for high-throughput digital signal and image processing", IEEE Trans. on Acoustics, Speech and Signal Processing, pp. 339-349, Vol 38, No 2, Feb 1990.

Crossref

Google Scholar

[9]

S. Note, F. Catthoor, G. Goossens, H. De Man, "Combined hardware selection and pipelining in high performance data-path design", IEEE international Conference on Computer Design, Sep 1990, Cambridge

Crossref

Google Scholar

[10]

S.Note, F.Catthoor, J.Van Meerbergen, H.De Man, "Definition and Assignment of Complex Data-Paths suited for High Throughput Applications", IEEE International Conference on Computer-Aided Design, Santa Clara, 6-9 November 1989.

Google Scholar

[11]

P.N.Hilfinger, "A high-level language and silicon compiler for digital signal processing", IEEE Custom Integrated Circuits Conf., Portland, May 1985.

Google Scholar

[12]

P.A. Kuetz, "Architectures and Design Techniques for Real Time Image Processing ICs", Phd. Thesis 1986.

Digital Library

Google Scholar

[13]

W. Geurts, S. Note, F. Catthoor, H. De Man, "Partltloning-based Allocation of Dedicated Datapaths in the Architectural Synthesis for High Throughput Applications", submitted to the VLSI Conf. 1991

Google Scholar

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Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications

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Published In

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

June 1991

783 pages

ISBN:0897913957

DOI:10.1145/127601

Chairman:
A. Richard Newton
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1991

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DAC91: The 28th ACM/IEEE Design Automation Conference

June 17 - 22, 1991

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Jemai MHassine SOuni BMtibaa A(2018)Optimization of Dynamic Power for System on Programmable Chip SOPCHandbook of Research on Power and Energy System Optimization10.4018/978-1-5225-3935-3.ch017(571-600)Online publication date: 2018
https://doi.org/10.4018/978-1-5225-3935-3.ch017
Kim H(2015)Wireless Communications Systems Design and ConsiderationsWireless Communications Systems Design10.1002/9781118759479.ch12(349-378)Online publication date: 7-Aug-2015
https://doi.org/10.1002/9781118759479.ch12
Eberle W(2008)Conclusions and Further ResearchWireless Transceiver Systems Design10.1007/978-0-387-74516-9_8(233-247)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_8
Eberle W(2008)Methodologies for Transceiver DesignWireless Transceiver Systems Design10.1007/978-0-387-74516-9_7(201-232)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_7
Eberle W(2008)Design Space Exploration for TransmittersWireless Transceiver Systems Design10.1007/978-0-387-74516-9_6(175-199)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_6
Eberle W(2008)Digital Compensation Techniques for Receiver Front-EndsWireless Transceiver Systems Design10.1007/978-0-387-74516-9_5(133-173)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_5
Eberle W(2008)Efficient Digital VLSI Signal Processing for OFDMWireless Transceiver Systems Design10.1007/978-0-387-74516-9_4(79-132)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_4
Eberle W(2008)Specification for a Wireless LAN TerminalWireless Transceiver Systems Design10.1007/978-0-387-74516-9_3(45-77)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_3
Eberle W(2008)The System Design ProcessWireless Transceiver Systems Design10.1007/978-0-387-74516-9_2(17-43)Online publication date: 2008
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