Article

Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits

Author:

Michael H. PerrottAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 498 - 503

https://doi.org/10.1145/513918.514045

Published: 10 June 2002 Publication History

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Abstract

Techniques for fast and accurate simulation of fractional-N synthesizers at a detailed behavioral level are presented. The techniques allow a uniform time step to be used for the simulator, and can be applied to a variety of phase locked loop (PLL) and delay locked loop (DLL) circuits beyond fractional-N synthesizers, as well as to a variety of simulation frameworks such as Verilog and Matlab. Simulated results from a custom C++ simulator are shown to compare well to measured results from a prototype fractional-N synthesizer using a Σ modulator to dither its divide value.

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Li YLin HLv JGao YDong W(2024)BLE Location Tracking Attacks by Exploiting Frequency Synthesizer ImperfectionIEEE INFOCOM 2024 - IEEE Conference on Computer Communications10.1109/INFOCOM52122.2024.10621247(1860-1869)Online publication date: 20-May-2024
https://doi.org/10.1109/INFOCOM52122.2024.10621247
Hati MBhattacharyya T(2017)A fast and efficient constant loop bandwidth with proposed PFD and pulse swallow divider circuit in ΔΣ fractional-N PLL frequency synthesizerMicroelectronics Journal10.1016/j.mejo.2016.12.01461(21-34)Online publication date: Mar-2017
https://doi.org/10.1016/j.mejo.2016.12.014
Abdallah MEladawy AMohieldin A(2015)An all-digital semi-blind clock and data recovery systemMicroelectronics Journal10.1016/j.mejo.2015.01.00646:4(273-284)Online publication date: Apr-2015
https://doi.org/10.1016/j.mejo.2015.01.006
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Index Terms

Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis

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Information & Contributors

Information

Published In

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 June 2002

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SIGDA

DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

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DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Li YLin HLv JGao YDong W(2024)BLE Location Tracking Attacks by Exploiting Frequency Synthesizer ImperfectionIEEE INFOCOM 2024 - IEEE Conference on Computer Communications10.1109/INFOCOM52122.2024.10621247(1860-1869)Online publication date: 20-May-2024
https://doi.org/10.1109/INFOCOM52122.2024.10621247
Hati MBhattacharyya T(2017)A fast and efficient constant loop bandwidth with proposed PFD and pulse swallow divider circuit in ΔΣ fractional-N PLL frequency synthesizerMicroelectronics Journal10.1016/j.mejo.2016.12.01461(21-34)Online publication date: Mar-2017
https://doi.org/10.1016/j.mejo.2016.12.014
Abdallah MEladawy AMohieldin A(2015)An all-digital semi-blind clock and data recovery systemMicroelectronics Journal10.1016/j.mejo.2015.01.00646:4(273-284)Online publication date: Apr-2015
https://doi.org/10.1016/j.mejo.2015.01.006
Brambilla ALinaro DStorace M(2012)Nonlinear behavioural model of charge pump PLLsInternational Journal of Circuit Theory and Applications10.1002/cta.181341:10(1027-1046)Online publication date: 2-Apr-2012
https://doi.org/10.1002/cta.1813
Zou JMueller DGraeb HSchlichtmann USentovich E(2006)A CPPLL hierarchical optimization methodology considering jitter, power and locking timeProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1146919(19-24)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1146919
Topaloglu R(2006)Monte Carlo-Alternative Probabilistic Simulations for Analog SystemsProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.90(249-253)Online publication date: 27-Mar-2006
https://dl.acm.org/doi/10.1109/ISQED.2006.90
Lau CPerrott MGetreu IFix LLavagno L(2003)Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithmProceedings of the 40th annual Design Automation Conference10.1145/775832.775966(526-531)Online publication date: 2-Jun-2003
https://dl.acm.org/doi/10.1145/775832.775966
Perrott M(2003)Design and Simulation of Fractional-N Frequency SynthesizersAnalog Circuit Design10.1007/0-306-48707-1_2(27-49)Online publication date: 2003
https://doi.org/10.1007/0-306-48707-1_2
Perrott M(2002)Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL CircuitsIEEE Design & Test10.1109/MDT.2002.101813619:4(74-83)Online publication date: 1-Jul-2002
https://dl.acm.org/doi/10.1109/MDT.2002.1018136

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