A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development

Regular Section

Mohammad ZALFANY URFIANTO, The Institute of Electronics, Information and Communication Engineers">Tsuyoshi ISSHIKI, Arif ULLAH KHAN, The Institute of Electronics, Information and Communication Engineers">Dongju LI, The Institute of Electronics, Information and Communication Engineers">Hiroaki KUNIEDA

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Keywords: multiprocessor-on-a-chip, system-on-chips, crossbar interconnect, VLSI

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2008 Volume E91.A Issue 4 Pages 1185-1196

DOI https://doi.org/10.1093/ietfec/e91-a.4.1185

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Abstract

This paper presentss a Multiprocessor System-on-Chips (MPSoC) architecture used as an execution platform for the new C-language based MPSoC design framework we are currently developing. The MPSoC architecture is based on an existing SoC platform with a commercial RISC core acting as the host CPU. We extend the existing SoC with a multiprocessor-array block that is used as the main engine to run parallel applications modeled in our design framework. Utilizing several optimizations provided by our compiler, an efficient inter-communication between processing elements with minimum overhead is implemented. A host-interface is designed to integrate the existing RISC core to the multiprocessor-array. The experimental results show that an efficacious integration is achieved, proving that the designed communication module can be used to efficiently incorporate off-the-shelf processors as a processing element for MPSoC architectures designed using our framework.

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