A New Low-Power 13.56-MHz CMOS Ring Oscillator with Low Sensitivity of fOSC to VDD

Special Section on Analog Circuit Techniques and Related Topics

A New Low-Power 13.56-MHz CMOS Ring Oscillator with Low Sensitivity of f_OSC to V_DD

The Institute of Electronics, Information and Communication Engineers">Felix TIMISCHL, The Institute of Electronics, Information and Communication Engineers">Takahiro INOUE, The Institute of Electronics, Information and Communication Engineers">Akio TSUNEDA, The Institute of Electronics, Information and Communication Engineers">Daisuke MASUNAGA

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Keywords: CMOS, ring oscillator, low power, g_m-booster, V_DD-dependency, composite transistor, figure of merit

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2008 Volume E91.A Issue 2 Pages 504-512

DOI https://doi.org/10.1093/ietfec/e91-a.2.504

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Abstract

A design of a low-power CMOS ring oscillator for an application to a 13.56MHz clock generator in an implantable RFID tag is proposed. The circuit is based on a novel voltage inverter, which is an improved version of the conventional current-source loaded inverter. The proposed circuit enables low-power operation and low sensitivity of the oscillation frequency, f_OSC, to decay of the power supply V_DD. By employing a g_m-boosting subcircuit, power dissipation is decreased to 49μW at f_OSC=13.56MHz. The sensitivity of f_OSC to V_DD is reduced to -0.02 at f_OSC=13.56MHz thanks to the use of composite high-impedance current sources.

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