Advanced Assertion-Based Design for Mixed-Signal Verification

Special Section on VLSI Design and CAD Algorithms

Alexander JESSER, Stefan LAEMMERMANN, Alexander PACHOLIK, Roland WEISS, Juergen RUF, Lars HEDRICH, Wolfgang FENGLER, Thomas KROPF, Wolfgang ROSENSTIEL

Author information

Alexander JESSER
Department of Computer Science, University of Frankfurt
Stefan LAEMMERMANN
Department of Computer Engineering, University of Tuebingen
Alexander PACHOLIK
Computer Architecture Group, Ilmenau Technical University
Roland WEISS
Industrial Software Systems, ABB Corporate Research
Juergen RUF
Department of Computer Engineering, University of Tuebingen
Lars HEDRICH
Department of Computer Science, University of Frankfurt
Wolfgang FENGLER
Computer Architecture Group, Ilmenau Technical University
Thomas KROPF
Department of Computer Engineering, University of Tuebingen
Wolfgang ROSENSTIEL
Department of Computer Engineering, University of Tuebingen

Keywords: assertions-based verification, mixed-signal simulation, simulation-based property checking, mixed-signal assertions, dynamic verification

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2008 Volume E91.A Issue 12 Pages 3548-3555

DOI https://doi.org/10.1093/ietfec/e91-a.12.3548

Details

Abstract

Functional and formal verification are important methodologies for complex mixed-signal design validation. However the industry is still verifying such systems by pure simulation. This process lacks on error localization and formal verifications methods. This is the existing verification gap between the analog and digital blocks within a mixed-signal system. Our approach improves the verification process by creating temporal properties named mixed-signal assertions which are described by a combination of digital assertions and analog properties. The proposed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a Σ/Δ-converter.

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