Low-Power Switched Current Memory Cell with CMOS-Type Configuration

Regular Section

The Institute of Electronics, Information and Communication Engineers">Masashi KATO, Presently, DENSOTECHNO CO., LTD.">Nobuyuki TERADA, Presently, OMRON Corporation">Hirofumi OHATA, Presently, Nagoya Institute of Technology
The Institute of Electronics, Information and Communication Engineers">Eisuke ARAI

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Keywords: switched current, low-power, CMOS-type, memory cell

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2008 Volume E91.C Issue 1 Pages 120-121

DOI https://doi.org/10.1093/ietele/e91-c.1.120

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Abstract

This letter presents a low-power switched current (SI) memory cell with CMOS-type configuration. By combining nMOS and pMOS in the SI memory cell and using a polarity discrimination circuit, we design a CMOS-type SI memory cell which eliminates the quiescent current in the SI memory cell. The simulation result shows that the CMOS-type SI memory cell consumes less power than the conventional class-AB memory cell.

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