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Leveraging controllability measures for high transition delay test coverage in DTESFF based partial enhanced scan design

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Abstract

Scan design is extensively exploited to test transition delay faults (TDF). Broadside test commonly referred as launch on capture and skewed load test is also commonly referred as launch-on-shift are two approaches to test TDF’s through scan design. However arbitrary test vector pair application is not supported by scan design because of architectural constraint of scan and this eventually limits the fault coverage for TDFs. Arbitrary test vector application is supported in enhanced scan design which alleviates the problem of poor fault coverage. Enhanced scan design has high area overhead and this problem can be further tackled through interchanging extra flip-flop by hold latch in enhanced scan. However hold signal required in enhanced scan design consists of hold latch is fast in nature. This signal is exactly equivalent of scan enable signal in skewed load test. Enhanced scan cell using one clock cycle slower hold signal is implemented in delay testable enhanced scan flip-flop (DTESFF) design. Partial enhanced scan method based on DTESFF design by using controllability measures for scan flip-flop identification is proposed for high transition delay test coverage in this work. Simulation results demonstrate the test coverage improvement for TDF in ISCAS 89 benchmark circuits.

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References

  • Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Kluwer Academic Publishers, Berlin

    Google Scholar 

  • Cheng KT, Devadas S, Keutzer KA (1991) Partial enhanced-scan approach to robust delay-fault test generation for sequential circuits. In: Proceedings of international test conference, pp 403–410

  • DasGupta et al. (1981) An enhancement to LSSD and some applications of LSSD in reliability, availability, and serviceability. In: International symposium on fault-tolerant computing, pp 32–34

  • Deepak KG, Reyna R, Singh V, Singh AD (2009) Leveraging partially enhanced scan for improved observability in delay fault testing. Asian test symposium, pp 237–240

  • Devtaprasanna N, Gunda A, Krishnamurthy P, Reddy SM, Pomeranz I (2005) Methods for improving transition delay fault coverage using broadside tests. In: Proceedings IEEE international test conference, pp 256–265

  • Devtaprasanna N, Gunda A, Krishnamurthy P, Reddy SM, Pomeranz I (2005) Improved delay fault coverage using subsets of flip-flops to launch transitions. In: Proceedings IEEE Asian test symposium, pp 202–207

  • EEDesign Article (2002) Delay-fault testing mandatory, author claims. https://www.eedesign.com/story/OEG20021204S0029

  • Goldstein LH, Thigpen EL (1980) SCOAP: sandia controllability/observability analysis program. In: Proceedings IEEE-ACM design automation conference, pp 190–196

  • Han C, Singh AD, Singh V (2011) Efficient partial enhanced scan for high coverage delay testing. In: proceeding of IEEE 43rd Southeastern symposium on system theory (SSST), pp 243–248

  • Hawkins C, Keshavarzi A, Segura J (2003) A view from the bottom: nanometer technology AC parametric failures—why, where, and how to detect. In: Proceedings of IEEE international symposium on defect and fault tolerance in VLSI systems, 2003, pp 267–276

  • Jayaram V, Saxena J , Butler K (2003) Scan-based transition-fault test can do job. EE Times

  • Kuppuswamy R et al (2004) Full hold-scan systems in microprocessors: cost/benefit analysis. Int Technol J 8:1

    Google Scholar 

  • Lin X, Press R, Rajski J, Reuter P, Rinderknecht T, Swanson B, Tamarapalli N (2003) High-frequency, at-speed scan testing. IEEE Des Test Comput 20(5):17–25

    Article  Google Scholar 

  • Mak T, Krstic A, Cheng KT, Wang L-C (2004) New challenges in delay testing of nanometer, multigigahertz designs. IEEE Des Test Comput 21(3):241–248

    Article  Google Scholar 

  • Mao W, Ciletti MD (1994) Reducing correlation to improve coverage of delay faults in scan-path design. IEEE Trans Comput Aided Des Integr Circ Syst 13(5):638–646

    Article  Google Scholar 

  • Menon S, Singh AD, Agrawal V (2009) Output hazard-free transition delay fault test generation. In: Proceedings of IEEE VLSI test symposium, May 2009, pp 97–102

  • Patil S, Savir J (1991) Skewed-load transition test. Part II: Coverage. Proc IEEE Int Test Conf 1992:714–722

    Google Scholar 

  • Pei S, Li H, Li X (2011) Flip-flop selection for partial enhanced scan to reduce transition test data volume. IEEE Trans Very Large Scale Integr Syst 99:1–13

    Google Scholar 

  • Savir J (1992) Skewed-load transition test: Part I, calculus. In: Proceedings of international test conference, pp 705–713

  • Savir J (1997) Scan latch design for delay test. In: Proceedings of international test conference, pp 446–452

  • Savir J, Patil S (1994) On broad-side delay test. In: Proceedings of VLSI test symposium (VTS’94), 1994, pp 284–290

  • Saxena J, Butler KM, Gatt J, Kumar RRSP, Basu S, Campbell DJ, Berech J (2002) Scan-based transition fault testing—implementation and low cost test challenges. In: Proceedings IEEE international test conference, pp 1120–1129

  • Suhag AK (2019) Reduction of test data volume using DTESFF-based partial enhanced scan method. In: Yadav N, Yadav A, Bansal J, Deep K, Kim J (eds) Harmony search and nature inspired optimization algorithms. Advances in intelligent systems and computing, vol 741. Springer, Singapore

    Google Scholar 

  • Suhag AK, Shrivastava V (2011) Delay testable enhanced scan flip–flop: DFT for high fault coverage. In: Proceedings of international symposium on electronic system design (ISED), pp 129–133

  • Suhag AK, Shrivastava V (2012) Performance evaluation of delay testable enhanced scan flip–flop. Int J Syst Assur Eng Manag 3(3):169–174

    Article  Google Scholar 

  • Suhag AK, Shrivastava V, Singh N (2013) Flip-flop selection for partial enhanced scan chain using DTESFF for high transition delay fault coverage. Int J Syst Assuran Eng 4(3):303–311

    Article  Google Scholar 

  • Tekumalla RC, Menon PR (1997) Delay testing with clock control: an alternative to enhanced scan. In: Proceedings of international test conference, pp 454–462

  • Wang S, Wei W (2008) Low overhead partial enhanced scan technique for compact and high fault coverage transition delay test patterns. In: proceedings of IEEE European test symposium, pp 125–130

  • Wang S, Liu X, Chakradhar ST (2004) Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets. In: Proceedings design automation and test in Europe conference and exhibition, pp 1296–1301

  • Xu G, Singh AD (2006) Low cost launch-on-shift delay test with slow scan enable. In: Proceedings of European test symposium

  • Xu G, Singh AD (2007) Flip-flop selection to maximize TDF coverage with partial enhanced scan. In: Proceedings of Asian test symposium, pp 335–340

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Correspondence to Vivek Shrivastava.

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Shrivastava, V., Suhag, A.K. Leveraging controllability measures for high transition delay test coverage in DTESFF based partial enhanced scan design. Int J Syst Assur Eng Manag 11, 655–661 (2020). https://doi.org/10.1007/s13198-020-00975-y

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  • DOI: https://doi.org/10.1007/s13198-020-00975-y

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