Abstract
Delay faults are regularly encountered in nanometric regime that’s why it is very important to detect these faults during the manufacturing test. Testing of delay fault requires two test vectors. In general delay faults are tested using scan-based designs. The second test vector is generated in scan either by broadside test (launch of capture test) or by skewed load test (launch-on-shift). Broadside test is preferred over skewed load test approach in designs because it is implemented by system clock for scan operations while skewed load delay test requires fast scan enable signal which is not supported by most of designs but skewed load delay test provides better transition delay fault coverage with fewer test patterns compared to broadside delay test. For maximum detection of delay faults it is essential that vectors in the pair should be independent. Due to structural limitation of scan independent test vector can’t be applied to the design, which results in degradation of delay test coverage. However this can be accomplished by the use of enhance scan flip-flop which presents the application of independent delay test vector pair at the cost of high area overhead and also requires fast hold signal, similar to scan enable signal in case of skewed load testing. This paper presents a new enhanced scan flip-flop design implemented with slow hold signal and we also discussed the performance penalty caused by the delay testable enhance scan flip-flop. Experimental results shows improvement in transition delay fault coverage on ISCAS 89 benchmark circuit with this method.
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References
Borkar S et al. (2003) Parameter variations and impact on circuits and microarchitecture. In: Proceeding of DAC, pp 338–342
Abraham J, Goel U, Kumar A (2006) Multi-cycle sensitizable transition delay faults. In: Proceedings of VLSI test symposium, pp 306–311
Brglez F, Bryan D, Koiminski K (1989) Combinational profiles of sequential benchmark circuits. In: Proceedings of IEEE international symposium on circuit and systems, pp 1929–1934
Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits, Springer
Chao H, Singh AD, Singh V (2011) Efficient partial enhanced scan for high coverage delay testing. In: Proceeding of IEEE 43rd southeastern symposium on system theory (SSST), pp 243–248
Cheng K-T et al (1991) A partial enhanced scan approach to robust delay-fault test generation for sequential circuits. ITC, Washington, DC, pp 403–410
Deepak KG, Reyna R, Singh V, Singh AD (2009) Leveraging partially enhanced scan for improved observability in delay fault testing. Asian Test Symposium, 2009, pp 237–240
Devtaprasanna N, Gunda A, Krishnamurthy P, Reddy SM, Pomeranz I (2005) Methods for improving transition delay fault coverage using broadside tests. In: Proceedings of international test conference, pp 256–265
EEDesign Article (2002) Delay-fault testing mandatory, author claims. http://www.eedesign.com/story/OEG20021204S0029. Accessed Jan 2011
EETimes Article (2003) Scan-based transition-fault test can do job. http://www.eetimes.com/story/OEG20031024S0028. Accessed Jan 2011
Hurst JP, Kanopoulos N (1995) Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits. In: Proceedings Asian test symposium, pp 346–352
Kumar R, Bollapalli KC, Garg R, Soni T, Khatri SP (2009) A robust pulsed flip-flop and its use in enhanced scan design. IEEE international conference on computer design (ICCD), pp 97–102
Namba K, Ikeda T, Ito H (2010) Construction of SEU tolerant flip-flops allowing enhanced scan delay fault testing. IEEE Trans Very Large Scale Integr VLSI Syst 18(9):1265–1276
Patil S, Savir J (1992) Skewed-load transition test: part II, coverage. In: Proceedings of international test conference, p 714
Pei S, Li H, Li X (2011) Flip-flop selection for partial enhanced scan to reduce transition test data volume. IEEE Trans Very Large Scale Integr (VLSI) Syst 99:1–13
Savir J (1992) Skewed-load transition test: part I, calculus. In: Proceedings of international test conference, p 705
Savir J (1997) Scan latch design for delay test. ITC, Washington, DC, pp 446–452
Savir J, Patil S (1994) On broad-side delay test. Very Large Scale Integr (VLSI) Syst 2:368
Saxena J, Butler KM, Gatt J, Raghuraman R, Kumar SP, Basu S, Campbell DJ, Berech J (2002) Scan-based transition fault testing—implementation and low cost test challenges. In: Proceedings of international test conference, pp 1120–1129
Seongmoon W, Xiao L, Chakradhar ST (2004) Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets. In: Proceedings of design, automation and test in Europe, pp 1296–1301
TekuMalla RC et al (1997) Delay testing with clock control: an alternative to enhanced scan. ITC, Washington, DC, pp 454–462
Waicukauski JA, Lindbloom E, Rosen B, Iyengar V (1987) Transition fault simulation. IEEE Des Test Comput 4:32–38
Wang S, Wei W (2008) Low overhead partial enhanced scan technique for compact and high fault coverage transition delay test patterns. In: Proceedings of European test symposium, pp 125–130
Wang S, Liu X, Chakradhar ST (2004) Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets. In: Proceedings of design, automation and test in Europe, pp 1296–1301
Xu G, Singh AD (2006) Low cost launch-on-shift delay test with slow scan enable. In: Proceedings of European test symposium, pp 9–14
Xu G, Singh AD (2007) Achieving high transition delay fault coverage with partial DTSFF scan chains. In: Proceedings of international test conference, pp 1–9
Zhang Z, Reddy SM, Pomeranz I, Lin X, Rajski J (2006) Scan tests with multiple fault activation cycles for delay faults. In: Proceedings of VLSI test symposium, pp 343–348
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Suhag, A.K., Shrivastava, V. Performance evaluation of delay testable enhanced scan flip-flop. Int J Syst Assur Eng Manag 3, 169–174 (2012). https://doi.org/10.1007/s13198-012-0124-7
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DOI: https://doi.org/10.1007/s13198-012-0124-7