Abstract
Terminal reliability of multistage interconnection network (MIN) is the probability of at least one fault free path between any source–destination nodes pair. MIN is used to interconnect processors and memory modules in multi-processor system. In this paper, terminal reliability is estimated and validated for existing MINs (i.e., SEN, SEN+, SEN+2, GIN, CGIN, PCGIN, 3D-GIN, 4D-GIN-1, 4D-GIN-2, 4D-GIN-3, and SEGINs). The comparison and performance analysis of MINs based on various indices are also presented.
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Authors acknowledge the National Institute of Technology Jamshedpur, India for providing the research opportunity and facilities.
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Prakash, A., Yadav, D.K. & Choubey, A. Terminal reliability analysis of multistage interconnection networks. Int J Syst Assur Eng Manag 11, 110–125 (2020). https://doi.org/10.1007/s13198-019-00929-z
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DOI: https://doi.org/10.1007/s13198-019-00929-z