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Design of INV/BUFF Logic Locking For Enhancing the Hardware Security

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Abstract

An increasingly popular method for defending an integrated circuit (IC) against theft, excess production, and the Hardware Trojans (HT) is logic locking. The majority of popular logical locking approaches were also susceptible to the SAT attacks. Although it has been reported that there are a number of SAT-resistant logical locking methods, such as Anti-SAT blocks (ASB), that lengthen the amount of time it takes to figure out the correct key, the current methods are possibly susceptible to removal attacks based on signal probability skew (SPS) or have a high design cost. It is suggested to use an INV/BUFF key model that produces an optimized design with less overhead than XOR/XNOR. The suggested method can significantly enhance logical locking without compromising security. Moreover, it reduces the area, power, and time overheads, respectively, by 2.76 %, 12.92 %, and 12.7 % in comparison to the XOR-based technique.

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Authors and Affiliations

  1. Department of ECE, Karunya Institute of Technology and Sciences, Coimbatore, Tamilnadu, 641114, India

    R. Naveenkumar, N. M. Sivamangai, A. Napolean, S. Sridevi Sathya Priya & S. V. Ashika

  2. Dept. of ECE, Karpagam Academy of Higher Education, Coimbatore, India

    R. Naveenkumar

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  1. R. Naveenkumar
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  2. N. M. Sivamangai
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  3. A. Napolean
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  4. S. Sridevi Sathya Priya
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  5. S. V. Ashika
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The first author wrote the manuscript, and the second author supervised, third, fourth and fifth author- done the proof reading.

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Correspondence to R. Naveenkumar.

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Naveenkumar, R., Sivamangai, N.M., Napolean, A. et al. Design of INV/BUFF Logic Locking For Enhancing the Hardware Security. J Electron Test 39, 141–153 (2023). https://doi.org/10.1007/s10836-023-06061-y

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