Abstract
This work presents an initiative to teach the basis of fault tolerance in digital systems design in undergraduate and graduate courses in electrical and computer engineering. The approach is based on a library of characteristic circuits related to fault tolerance techniques which has been implemented using a Hardware Description Language (VHDL). Due to the properties of the design tools associated to these languages, this approach allows with ease: (1) to implement faults tolerant digital systems; (2) to d etermine the behaviour of system when faults are presented; (3) to evaluate the additional resources and response time linked to any fault tolerance technique in the laboratory.
This work was supported by the Ministry of Education of Spain (TIC2002-00228)
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Ortigosa, P.M., López, O., Estrada, R., García, I., Garzón, E.M. (2003). A VHDL Library to Analyse Fault Tolerant Techniques. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_114
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DOI: https://doi.org/10.1007/978-3-540-45234-8_114
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