Abstract
This chapter explores the key aspects of near-threshold operation. Technology constraints, building blocks and architectural aspects for operating circuits at ultra-low voltage are discussed. All the simulations and prototypes developed in Chap. 2–6 were acquired using a 40-nm CMOS technology. The transistor behaviour of said technology is the base of all the design considerations made further on. Section 2.1 lays out the ground work for this: transistor operating regions, device sizing, FO4 inverter performance and others are presented. These analyses enable an intuitive but surprisingly accurate insight in the microcontroller prototypes developed further in this work.
The logic gate topology used across all the prototypes presented in this work is the differential transmission gate. Section 2.2 looks at the different aspects influencing this choice and compares with other approaches. The VLSI design methodology motivates us to use sequential clock edge triggered pipelines. The flip-flop building block used in this work is briefly discussed in Sect. 2.3, together with some considerations on how it impacts the microcontroller prototypes.
Architectural properties of a digital system equally influence the system’s ultra-low voltage performance and minimum energy design target. Pipeline depth and circuit activity are important considerations. Their influence is discussed in Sect. 2.4. The impact of recent advancements in CMOS technology is briefly discussed in Sect. 2.5.
Every section of this chapter briefly sketches the application of the discussed considerations by looking forward to the prototypes of Chaps. 4 and 6. In doing so, the considerations made in this chapter and the conclusions presented in Sect. 2.6 become more tangible.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
From this point on simulations use the near-threshold optimized stacked nMOS inverter as shown in Fig. 2.20.
- 2.
As discussed in Chap. 1, dynamic power is proportional to \({V_{\mathrm {{dd}^{2}}}}\), which is the main motivation for near-threshold operation.
- 3.
The actual activity rate depends as much on the incoming data as on the amount of pipeline stages.
References
Alarcón, L.P., Liu, T.T., Pierson, M.D., Rabaey, J.M.: Exploring very low-energy logic: a case study. J. Low Power Electron. 3, 223–233 (2007)
Bol, D., Hocquet, C., Flandre, D., Legat, J.D.: The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic. In: 36th IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 522–525. IEEE, Piscataway (2010)
Bol, D., De Vos, J., Hocquet, C., Botman, F., Durvaux, F., Boyd, S., Flandre, D., Legat, J.D.: SleepWalker: a 25-MHz 0.4-V sub-mm2 7-uW/MHz microcontroller in 65-nm LP/GP CMOS for low-carbon wireless sensor nodes. IEEE J. Solid State Circuits 48(1), 20–32 (2013)
Dreslinski, R.G., Wieckowski, M., Blaauw, D., Sylvester, D., Mudge, T.: Near-threshold computing: reclaiming Moore’s law through energy efficient integrated circuits. Proc. IEEE 98(2), 253–266 (2010)
Jacquet, D., Hasbani, F., Flatresse, P., Wilson, R., Arnaud, F., Cesana, G., Di Gilio, T., Lecocq, C., Roy, T., Chhabra, A., Grover, C., Minez, O., Uginet, J., Durieu, G., Adobati, C., Casalotto, D., Nyer, F., Menut, P., Cathelin, A., Vongsavady, I., Magarshack, P.: A 3 GHz dual core processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS with ultra-wide voltage range and energy efficiency optimization. IEEE J. Solid State Circuits 49(4), 812–826 (2014)
Jeon, D., Seok, M., Chakrabarti, C., Blaauw, D., Sylvester, D.: A super-pipelined energy efficient subthreshold 240 MS/s FFT core in 65 nm CMOS. IEEE J. Solid State Circuits 47(1), 23–34 (2012)
Jin, W., Kim, S., He, W., Mao, Z., Seok, M.: In situ error detection techniques in ultralow voltage pipelines: analysis and optimizations. IEEE Trans. Very Large Scale Integr. VLSI Syst. 25(3), 1032–1043 (2017)
Kim, J.J., Roy, K.: Double gate-MOSFET subthreshold circuit for ultralow power applications. IEEE Trans. Electron Devices 51(9), 1468–1474 (2004)
Kwong, J., Ramadass, Y.K., Verma, N., Chandrakasan, A.P.: A 65 nm sub-Vt microcontroller with integrated SRAM and switched capacitor DC-DC converter. IEEE J. Solid State Circuits 44(1), 115–126 (2009)
Lim, W., Lee, I., Sylvester, D., Blaauw, D.: Batteryless sub-nW cortex-M0+ processor with dynamic leakage-suppression logic. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 1–3. IEEE, Piscataway (2015)
Luetkemeier, S., Jungeblut, T., Porrmann, M., Rueckert, U.: A 200mV 32b subthreshold processor with adaptive supply voltage control. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 484–486. IEEE, Piscataway (2012)
Mäkipää, J., Turnquist, M.J., Laulainen, E., Koskinen, L.: Timing-error detection design considerations in subthreshold: an 8-bit microprocessor in 65 nm CMOS. J. Low Power Electr. Appl. 2(2), 180–196 (2012)
Markovic, D., Wang, C., Alarcon, L., Tsung-Te Liu, Rabaey, J.: Ultralow-power design in near-threshold region. Proc. IEEE 98(2), 237–252 (2010)
Myers, J., Savanth, A., Howard, D., Gaddh, R., Prabhat, P., Flynn, D.: An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65 nm CMOS for WSN applications. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 1–3. IEEE, Piscataway (2015)
Paul, S., Honkote, V., Kim, R.G., Majumder, T., Aseron, P.A., Grossnickle, V., Sankman, R., Mallik, D., Wang, T., Vangal, S., Tschanz, J.W., De, V.: A sub-cm3 energy-harvesting stacked wireless sensor node featuring a near-threshold voltage IA-32 microcontroller in 14-nm tri-gate CMOS for always-ON always-sensing applications. IEEE J. Solid State Circuits 52(4), 961–971 (2017)
Pinckney, N., Shifren, L., Cline, B., Sinha, S., Jeloka, S., Dreslinski, R.G., Mudge, T., Sylvester, D., Blaauw, D.: Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability. In: Proceedings of the 53rd Annual Design Automation Conference (DAC), pp. 1–6. IEEE, New York (2016)
Rabaey, J., Chandrakasan, A.P., Nikolic, B.: Digital Integrated Circuits: A Design Perspective, 2nd edn. Pearson Education Inc., Hoboken (2003)
Razavi, B.: Design of Analog CMOS Integrated Circuits, 2nd edn. McGraw Hill Education, New York (2017)
Reynders, N., Dehaene, W.: A 190mV supply, 10MHz, 90 nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques. In: IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 113–116. IEEE, Piscataway (2011)
Reynders, N., Dehaene, W.: Variation-resilient building blocks for ultra-low-energy sub-threshold design. IEEE Trans. Circuits Syst. Express Briefs 59(12), 898–902 (2012)
Reynders, N., Dehaene, W.: Variation-resilient sub-threshold circuit solutions for ultra-low-power digital signal processors with 10MHz clock frequency. In: 38th IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 474–477. IEEE, Piscataway (2012)
Reynders, N., Dehaene, W.: A 210mV 5MHz variation-resilient near-threshold JPEG encoder in 40 nm CMOS. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 456–457. IEEE, Piscataway (2014)
Reynders, N., Dehaene, W.: Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits. Springer, Leuven (2015)
Reyserhove, H., Dehaene, W.: A 16.07pJ/cycle 31MHz fully differential transmission gate logic ARM Cortex M0 core in 40 nm CMOS. In: 42nd IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 257–260. IEEE, Piscataway (2016)
Reyserhove, H., Dehaene, W.: A differential transmission gate design flow for minimum energy sub-10-pJ/cycle ARM Cortex-M0 MCUs. IEEE J. Solid State Circuits 52(7), 1904–1914 (2017)
Reyserhove, H., Reynders, N., Dehaene, W.: Ultra-low voltage datapath blocks in 28 nm UTBB FD-SOI. In: IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 49–52. IEEE, Piscataway (2014)
Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91(2), 305–327 (2003)
Soeleman, H., Roy, K.: Ultra-low power digital subthreshold logic circuits. In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 94–96. ACM Press, New York (1999)
Tae-Hyoung Kim, Keane, J., Hanyong Eom, Kim, C.: Utilizing reverse short-channel effect for optimal subthreshold circuit design. IEEE Trans. Very Large Scale Integr. VLSI Syst. 15(7), 821–829 (2007)
Tsividis, Y., McAndrew, C.: Operation and Modeling of the MOS Transistor, 3rd edn. Oxford University Press, London (2011)
Wang, A., Calhoun, B.H., Chandrakasan, A.P.: Sub-threshold Design for Ultra Low Power Systems. Springer, New York (2006)
Weste, N., Harris, D.: CMOS VLSI Design: A Circuits and Systems Perspective, 4th edn. Addison-Wesley Publishing, Boston (2010)
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Reyserhove, H., Dehaene, W. (2019). Near-Threshold Operation: Technology, Building Blocks and Architecture. In: Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors. Springer, Cham. https://doi.org/10.1007/978-3-030-12485-4_2
Download citation
DOI: https://doi.org/10.1007/978-3-030-12485-4_2
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-12484-7
Online ISBN: 978-3-030-12485-4
eBook Packages: EngineeringEngineering (R0)