Abstract
This work tries to combine the described challenges that energy-efficient microcontrollers face in sub-micron CMOS technologies. An ultra-low energy consumption with fast enough performance while being variation-resilient is the triple combination this work targets. Ideally, this system is realized using an efficient design process that helps the designer to improve the system as much as possible. To accomplish this, variation-resilient building blocks and design techniques to operate at ultra-low voltage are presented. This results in the efficient implementation of several microcontroller prototypes fabricated in 40 nm CMOS technology that achieve state-of-the-art performance and ultra-low energy consumption. This chapter gives a short overview of the main challenges faced in this work, and thereby introduces the remaining chapters. First, the concept of minimum energy operation is introduced. It is the main target for everything developed in this work. Second, CMOS technology and the problems it faces when operated for minimum energy are discussed. Third, efficient design through a standard cell based very-large-scale-integration (VLSI) design flow is elaborated on. Variations and their influence are the fourth topic. Fifth, current and possible future applications for microcontrollers and other systems that benefit from minimum energy operation and variation-resilient design are discussed. These topics set out the main challenges this work faces. Finally, the goals this work aims for are defined.
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Reyserhove, H., Dehaene, W. (2019). Energy-Efficient Processors: Challenges and Solutions. In: Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors. Springer, Cham. https://doi.org/10.1007/978-3-030-12485-4_1
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DOI: https://doi.org/10.1007/978-3-030-12485-4_1
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