Abstract
This paper presents an analytical model for the performance of a generic reconfigurable coprocessor (RC) system. The system is characterized by a standard processor with a portion that is reconfigurable. We describe a general performance model for the speedup of a generic RC system. We demonstrate how different parameters of speedup model can affect the performance of reconfigurable system (RS). In addition, we implement our pre-developed speedup model for a system that allows preloading of the functional blocks (FB) into the reconfigurable hardware (RH). The redevelopment of speedup model with the consideration of preloading demonstrates some interesting results that can be used to improve the performance of RH with a coprocessor. Finally, we develop a performance model for a specific application. The application is characterized by a main iterative loop in which a core operation is to be defined in a FB. Our experiments show that the minimum and maximum speedup mainly depends on the probabilities of miss and hit for the FB that resides in the RH of a coprocessor. In addition, our simulation results for application specific model demonstrate how the probability of dependency degrades the achievable speedup.
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References
A. DeHon ™Architectures for General-Purpose Computing, “A.I. Technical Report,” No. 1586, Artificial Intelligence Laboratory, MIT.
Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J, Kurdahi, and Nader Bagherzadeh, “MorphoSys - An Integrated Reconfigurable System for Data Parallel Computation-Intensive Applications,” University of California, Irvine, CA 92697.
T. J. Callahan, J. R. Kouser, and J. Wawrzynek, “The GARP Architecture and C Compiler,” IEEE Computer, 33(4):62-69 2000.
Y. Chou, P. Pillai, H. Schmit, and J. P. Shen, “Pipe-Rench Implementation of the Instruction Path Coprocessor,” Int. Symp. On Micro-architecture, pp.147-158, 2000.
Scott Hauck, Thomas W. Fry, Matthew M. Hosler, and Jeffrey P. Kao, “The Chimaera Reconfigurable Functional Unit,” IEEE Symposium on FPGAs for Custom Computing Machines, 1997. Available: http://citeseer.ist.psu.edu/hauck97chimaera.html
Vishal Choudhary, A. Wel, M. Bekooij, and J. Huisken, “Reconfigurable Architecture for Multi-Standard Audio Codecs,” Philips Research Labs. The Netherlands. Available: http://wwwhome.cs.utwente.nl/$∼$smit/HWSWcodesign/paper_choudhary.pdf
J. R. Hauser and J. Wawrzynek, “GARP: A MIPS processor with a reconfigurable coprocessor,” in IEEE Workshop on FPGAs for Custom Computing Machines, pp.24–33, 1997. Available: http://citeseer.ist.psu.edu/hauser97garp.html
T. Miyamori, and K. Olukotun, “A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications,” IEEE Symp. On FCCM, 1998.
Seth C. Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, and Ronald Laufer, "Piperench: A coprocessor for streaming multimedia acceleration," In Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 28-39, May 1999.
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Rizvi, S.S., Hyder, S.N., Riasat, A. (2008). Performance Model for a Reconfigurable Coprocessor. In: Sobh, T. (eds) Advances in Computer and Information Sciences and Engineering. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8741-7_91
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DOI: https://doi.org/10.1007/978-1-4020-8741-7_91
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