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DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips

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Handbook of Hardware/Software Codesign

Abstract

The complexity of modern embedded systems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of system-level design. To cope with this design complexity, system-level design aims at raising the abstraction level of the design process from the register-transfer level (RTL) to the so-called electronic system level (ESL). However, this opens a large gap between deployed ESL models and RTL implementations of the MPSoC under design, known as the implementation gap. Therefore, in this chapter, we present the Daedalus methodology which the main objective is to bridge this implementation gap for the design of streaming embedded MPSoCs. Daedalus does so by providing an integrated and highly automated environment for application parallelization, system-level design space exploration, and system-level hardware/software synthesis and code generation.

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Abbreviations

ADG:

Approximated Dependence Graph

CC:

Communication Controller

CM:

Communication Memory

DCT:

Discrete Cosine Transform

DMA:

Direct Memory Access

DSE:

Design Space Exploration

DWT:

Discrete Wavelet Transform

ESL:

Electronic System Level

FCFS:

First-Come First-Serve

FIFO:

First-In First-Out

FPGA:

Field-Programmable Gate Array

GA:

Genetic Algorithm

GCC:

GNU Compiler Collection

GUI:

Graphical User Interface

HW:

Hardware

IP:

Intellectual Property

IPM:

Intellectual Property Module

ISA:

Instruction-Set Architecture

JPEG:

Joint Photographic Experts Group

KPN:

Kahn Process Network

MIR:

Medical Image Registration

MJPEG:

Motion JPEG

MoC:

Model of Computation

MPSoC:

Multi-Processor System-on-Chip

OS:

Operating System

PIP:

Parametric Integer Programming

PN:

Process Network

PPN:

Polyhedral Process Network

RTL:

Register Transfer Level

SANLP:

Static Affine Nested Loop Program

STree:

Schedule Tree

SW:

Software

UART:

Universal Asynchronous Receiver/Transmitter

VHDL:

VHSIC Hardware Description Language

VHSIC:

Very High Speed Integrated Circuit

XML:

Extensible Markup Language

YML:

Y-chart Modeling Language

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Authors and Affiliations

  1. Leiden University, Niels Bohrweg 1, 2333 CA, Leiden, The Netherlands

    Todor Stefanov & Hristo Nikolov

  2. University of Amsterdam, Science Park 904, 1098 XH, Amsterdam, The Netherlands

    Andy Pimentel

Authors
  1. Todor Stefanov
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  2. Andy Pimentel
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  3. Hristo Nikolov
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Correspondence to Todor Stefanov .

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Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

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Stefanov, T., Pimentel, A., Nikolov, H. (2017). DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_30

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