STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier

Special Section on VLSI Design and CAD Algorithms

Yohei UMEKI, Koji YANAGIDA, Shusuke YOSHIMOTO, Shintaro IZUMI, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI, Koji TSUNODA, Toshihiro SUGII

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Keywords: STT-MRAM, low-voltage, process-variation-tolerant

JOURNAL RESTRICTED ACCESS

2014 Volume E97.A Issue 12 Pages 2411-2417

DOI https://doi.org/10.1587/transfun.E97.A.2411

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Abstract

This paper reports a 65nm 8Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation-tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSs as loads, which maximizes the readout margin at any process corner. The STT-MRAM achieves a cycle time of 1.9µs (=0.526MHz) at 0.38V. The operating power is 1.70µW at this voltage. The minimum energy per access is 1.12 pJ/bit when the supply voltage is 0.44V. The proposed STT-MRAM operates at a lower energy than an SRAM when the utilization of the memory bandwidth is 14% or less.

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