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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on Design Methodologies for System on a Chip
NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time
JST, CREST">Hiroaki KONOURA JST, CREST">Toshihiro KAMEDA School of Systems Engineering, Kochi University of Technology">Yukio MITSUYAMA JST, CREST">Masanori HASHIMOTO JST, CREST">Takao ONOYE
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2014 Volume E97.A Issue 7 Pages 1483-1491

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Abstract

Negative Bias Temperature Instability (NBTI) is one of the serious concerns for long-term circuit performance degradation. NBTI degrades PMOS transistors under negative bias, whereas they recover once negative bias is removed. In this paper, we propose a mitigation method for NBTI-induced performance degradation that exploits the recovery property by shifting random input sequence through scan paths. With this method, we prevent consecutive stress that causes large degradation. Experimental results reveal that random scan-in vectors successfully mitigate NBTI and the path delay degradation is reduced by 71% in a test case when standby mode occupies 10% of total time. We also confirmed that 8-bit LFSR is capable of random number generation for this purpose with low area and power overhead.

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© 2014 The Institute of Electronics, Information and Communication Engineers
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