This paper discusses the impact of stacking on-chip inductor on power/ground network. Stacking inductor on other circuit components can reduce the circuit area drastically, however, the impact on signal and power integrity is not clear. We investigate the impact by a field-solver, a circuit simulator and real chip measurement. We evaluate three types of power/ground network and various multi-layered inductors. Experimental results show that dense power/ground structures reduce noise although the coupling capacitance becomes larger than that of sparse structures. Measurement in a 65-nm CMOS shows a woven structure makes the noise voltage half compared to a sparse structure.