LETTER
A 10.31 ENOB 3.125MHz BW fully passive 2nd-order noise-shaping SAR ADC for low cost IoT sensor networks
2024 Volume 21 Issue 1 Pages 20230122
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2024 Volume 21 Issue 1 Pages 20230122
This paper presents a fully passive 2nd-order noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) designed specifically for low-power and low-cost Internet of Things (IoT) applications. By optimizing the coefficients, a substantial 24dB in-band quantization noise suppression is achieved. To further reduce power consumption and the total unit capacitor count, a hybrid switching procedure and optimal logic are utilized. The measurement result shows that this design achieves an effective number of 10.31 bits over a 3.125MHz signal bandwidth. At a power supply of 1.8V, the power consumption is measured to be 728µW with a sampling rate of 50MS/s. Fabricated in 180-nm CMOS technology, the ADC core occupies an area of 0.117mm2. The Schrier figure-of-merit (FoM) of 160.13dB is obtained.