2021 Volume 18 Issue 9 Pages 20210070
Power delivery network (PDN) impedance reduction is strongly required for recent high-performance graphical-processing-unit, and mobile electronics that requires massive data transfer among logic and memory dice. To improve PDN characteristics, low equivalent series inductance and resistance (ESL and ESR) are required for capacitor, as well as powerline routing including placement of the capacitor. In this paper, we focus on Si-interposer as a method to enable ultra-high bit rate as well as fan-out wafer level packaging. A Si-interposer with transmission lines is manufactured, and CMOS test vehicle and low ESL Si-capacitors are mounted on the Si-interposer to evaluate chip-to-chip communication performance on multi-chip-module (MCM), through evaluating powerline noise. Experimental results of in-place waveform with physically different capacitor types and placements on Si-interposer, by on-chip waveform monitoring (OCM) technology. PDN analysis clarified the efficacy of low profile Si-capacitors and placement strategy to minimize series parasitic components, captured waveform shows stabilized drain power voltage (VDD) waveshape through 12-channels low-voltage differential signaling (LVDS) transceivers operation.