Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

LETTER

National Institution of Advanced Industrial Science and Technology (AIST)">Trong-Thuc Hoang, Ckristian Duran, The University of Danang, University of Science and Technology (DUT)">Khai-Duy Nguyen, The University of Danang, University of Science and Technology (DUT)">Tuan-Kiet Dang, Quynh Nguyen Quang Nhu, Phuc Hong Than, Xuan-Tu Tran, Duc-Hung Le, Akira Tsukamoto, Technology Research Association of Secure IoT Edge application based on RISC-V Open architecture (TRASIO)">Kuniyasu Suzaki, Cong-Kha Pham

Author information

Trong-Thuc Hoang
University of Electro-Communications (UEC)
National Institution of Advanced Industrial Science and Technology (AIST)
Ckristian Duran
University of Electro-Communications (UEC)
Khai-Duy Nguyen
University of Electro-Communications (UEC)
The University of Danang, University of Science and Technology (DUT)
Tuan-Kiet Dang
University of Electro-Communications (UEC)
The University of Danang, University of Science and Technology (DUT)
Quynh Nguyen Quang Nhu
The University of Danang, University of Science and Technology (DUT)
Phuc Hong Than
Duy Tan University (DTU)
Xuan-Tu Tran
University of Engineering and Technology (VNU-UET)
Duc-Hung Le
University of Science (VNU-HCMUS)
Akira Tsukamoto
National Institution of Advanced Industrial Science and Technology (AIST)
Kuniyasu Suzaki
National Institution of Advanced Industrial Science and Technology (AIST)
Technology Research Association of Secure IoT Edge application based on RISC-V Open architecture (TRASIO)
Cong-Kha Pham
University of Electro-Communications (UEC)

Keywords: 32-bit microcontroller, back-gate bias, RISC-V, RV32IM, Silicon-on-Insulator, SOTB

JOURNAL FREE ACCESS

2020 Volume 17 Issue 20 Pages 20200282

DOI https://doi.org/10.1587/elex.17.20200282

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Abstract

In this paper, a 32-bit RISC-V microcontroller in a 65-nm Silicon-On-Thin-BOX (SOTB) chip is presented. The system is developed based on the VexRiscv Central Processing Unit (CPU) with the Instruction Set Architecture (ISA) extensions of RV32IM. Besides the core processor, the System-on-Chip (SoC) contains 8KB of boot ROM, 64KB of on-chip memory, UART controller, SPI controller, timer, and GPIOs for LEDs and switches. The 8KB of boot ROM has 7KB of hard-code in combinational logics and 1KB of a stack in SRAM. The proposed SoC performs the Dhrystone and Coremark benchmarks with the results of 1.27 DMIPS/MHz and 2.4 Coremark/MHz, respectively. The layout occupies 1.32-mm² of die area, which equivalents to 349,061 of NAND2 gate-counts. The 65-nm SOTB process is chosen not only because of its low-power feature but also because of the back-gate biasing technique that allows us to control the microcontroller to favor the low-power or the high-performance operations. The measurement results show that the highest operating frequency of 156-MHz is achieved at 1.2-V supply voltage (V_DD) with +1.6-V back-gate bias voltage (V_BB). The best power density of 33.4-µW/MHz is reached at 0.5-V V_DD with +0.8-V V_BB. The least current leakage of 3-nA is retrieved at 0.5-V V_DD with -2.0-V V_BB.

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