Nothing Special   »   [go: up one dir, main page]

IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors
Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences">Qian Di Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences">Zhongxing Zhang Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences">Honglong Li Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences">Zhao Zhang Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences">Peng Feng Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences
Center for Excellence in Brain Science and Intelligence Technology, Chinese Academy of Sciences">Nanjian Wu
Author information
JOURNAL FREE ACCESS

2019 Volume 16 Issue 21 Pages 20190544

Details
Abstract

This paper proposes novel single event upset (SEU) failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors. To automatically evaluate the SEU failure probability and identify all the critical elements in a processor, complementary fault injection methods based on logic circuit simulator and Perl script are proposed. These methods can be used to randomly inject faults into D flip-flops (DFFs) and various types of memory at the register transfer level (RTL) as well as to evaluate the vision processor performance. Based on the evaluation results, an accurate periodic scrubbing technique is proposed to increase the processor availability. The results denote that the peak availability of the processor over a period of one year can be improved from 18% to 99.9% after scrubbing the RISC program memory for a period of 104 s. Therefore, we can improve the fault-tolerance performance of a vision processor while avoiding unnecessary area and power costs using techniques ranging from evaluation to mitigation.

Content from these authors
© 2019 by The Institute of Electronics, Information and Communication Engineers
Previous article Next article
feedback
Top