Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process

LETTER

University of Chinese Academy of Sciences">Yuan Du, University of Chinese Academy of Sciences">Yong Ye, Weiliang Jing, University of Chinese Academy of Sciences">Xiaoyun Li, Zhitang Song, Bomy Chen

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Keywords: logic area reduction, NSL, DTI, STI, 40 nm emPCM process

JOURNAL FREE ACCESS

2017 Volume 14 Issue 15 Pages 20170628

DOI https://doi.org/10.1587/elex.14.20170628

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Abstract

There is a growing demand for embedded non-volatile memory (eNVM) in Internet of Things (IoTs). Phase change memory (PCM) is a promising candidate for next generation eNVM with excellent CMOS process compatibility. Deep trench isolation (DTI) process is one of the extra steps to generate the diode selectors for PCM cells under 40 nm CMOS process. In this paper, we propose a 40 nm Non-volatile Standard cell Library (NSL) by reusing the DTI process to minimize the space among active areas. Thus, benefit from the embedded PCM (emPCM) process, the area of logic circuits can be reduced by using NSL. To verify the validity of the NSL, four ring oscillators are fabricated by using the normal standard cell library and NSL. The measured results show that the circuits by NSL work well and there is almost no performance sacrifice.

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