This paper presents a 10-Gb/s low-power adaptive continuous-time linear equalizer, which automatically determines the optimal equalization condition by searching for the equalization coefficient producing the largest peak value in histograms obtained with asynchronous under-sampling. To reduce the power consumption, the integrated digital controller turns off the circuit blocks used for the adaptation process once adaptation is complete. A prototype equalizer realized in 65-nm CMOS technology consumes 4.66mW during adaptation and 2.49mW after adaptation. For 10-Gb/s 2³¹−1 PRBS data transmitted over 40-cm FR4 PCB trace, our equalizer achieves less than 10⁻¹³ BER and 26.6ps peak-to-peak jitter.