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Johann Knechtel
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2020 – today
- 2024
- [j27]Gino A. Chacon
, Charles Williams
Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems. ACM Trans. Archit. Code Optim. 21(2): 23 (2024) - [j26]Rupesh Raj Karn
Progressive Learning With Recurrent Neural Network for Sequence Classification. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1591-1595 (2024) - [c36]Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu:
Obfuscation of FSMs for Secure Outsourcing of Neural Network Inference onto FPGAs. ISCAS 2024: 1-5 - [c35]Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu:
Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End Methodology. ISQED 2024: 1-8 - [c34]Zeng Wang, Lilas Alrahis, Likhitha Mankali, Johann Knechtel, Ozgur Sinanoglu:
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust. ISVLSI 2024: 385-390 - [i41]Jitendra Bhandari, Mohammed Thari Nabeel, Likhitha Mankali, Ozgur Sinanoglu, Ramesh Karri, Johann Knechtel:
Lightweight Masking Against Static Power Side-Channel Attacks. CoRR abs/2402.03196 (2024) - [i40]Fangzhou Wang, Qijing Wang, Lilas Alrahis, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Ozgur Sinanoglu, Tsung-Yi Ho, Evangeline F. Y. Young, Johann Knechtel:
TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans. CoRR abs/2405.05590 (2024) - [i39]Zeng Wang, Lilas Alrahis, Likhitha Mankali, Johann Knechtel, Ozgur Sinanoglu:
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust. CoRR abs/2405.07061 (2024) - [i38]Jitendra Bhandari, Johann Knechtel, Ramesh Narayanaswamy, Siddharth Garg, Ramesh Karri:
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines. CoRR abs/2406.17132 (2024) - [i37]Jitendra Bhandari, Animesh Basak Chowdhury, Mohammed Nabeel, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri, Johann Knechtel:
ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. CoRR abs/2406.19549 (2024) - [i36]Prithwish Basu Roy, Johann Knechtel, Akashdeep Saha, Saideep Sreekumar, Likhitha Mankali, Mohammed Thari Nabeel, Debdeep Mukhopadhyay, Ramesh Karri, Ozgur Sinanoglu:
NiLoPher: Breaking a Modern SAT-Hardened Logic-Locking Scheme via Power Analysis Attack. IACR Cryptol. ePrint Arch. 2024: 309 (2024) - [i35]Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini:
Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Cryptol. ePrint Arch. 2024: 1440 (2024) - 2023
- [j25]Likhitha Mankali
VIGILANT: Vulnerability Detection Tool Against Fault-Injection Attacks for Locking Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3571-3584 (2023) - [j24]Likhitha Mankali
Titan: Security Analysis of Large-Scale Hardware Obfuscation Using Graph Neural Networks. IEEE Trans. Inf. Forensics Secur. 18: 304-318 (2023) - [c33]Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu:
Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs. ASP-DAC 2023: 83-90 - [c32]Animesh Basak Chowdhury, Lilas Alrahis, Luca Collini, Johann Knechtel, Ramesh Karri
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning. DAC 2023: 1-6 - [c31]Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu:
TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection. ISCAS 2023: 1-5 - [c30]Fangzhou Wang
Security Closure of IC Layouts Against Hardware Trojans. ISPD 2023: 229-237 - [c29]Saideep Sreekumar
X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks. ISPD 2023: 238-246 - [c28]Mohammad Eslami
Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 Contest. ISPD 2023: 256-264 - [c27]Lilas Alrahis, Likhitha Mankali, Satwik Patnaik, Abhrajit Sengupta, Johann Knechtel, Ozgur Sinanoglu:
UN-SPLIT: Attacking Split Manufacturing Using Link Prediction in Graph Neural Networks. SPACE 2023: 197-213 - [i34]Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu:
TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection. CoRR abs/2301.11804 (2023) - [i33]Animesh Basak Chowdhury, Lilas Alrahis, Luca Collini
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning. CoRR abs/2303.03372 (2023) - [i32]Jitendra Bhandari, Jayanth Gopinath, Mohammed Ashraf, Johann Knechtel, Ramesh Karri
DEFending Integrated Circuit Layouts. IACR Cryptol. ePrint Arch. 2023: 205 (2023) - [i31]Jitendra Bhandari, Likhitha Mankali, Mohammed Nabeel, Ozgur Sinanoglu, Ramesh Karri
Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks. IACR Cryptol. ePrint Arch. 2023: 920 (2023) - 2022
- [j23]Gino A. Chacon
Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems. IEEE Comput. Archit. Lett. 21(2): 133-136 (2022) - [j22]Abhrajit Sengupta, Mohammed Nabeel, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu:
A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. Cryptogr. 6(2): 22 (2022) - [j21]Nikhil Rangarajan
SuperVAULT: Superparamagnetic Volatile Auxiliary Tamper-Proof Storage. IEEE Embed. Syst. Lett. 14(2): 103-106 (2022) - [j20]Johann Knechtel
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology. Integr. 85: 27-34 (2022) - [j19]Satwik Patnaik
Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(2): 266-280 (2022) - [j18]Lilas Alrahis
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2435-2448 (2022) - [j17]Lilas Alrahis
GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 3826-3837 (2022) - [j16]Nikhil Rangarajan
A Novel Attack Mode on Advanced Technology Nodes Exploiting Transistor Self-Heating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4134-4144 (2022) - [j15]Nikhil Rangarajan
Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices. IEEE Trans. Emerg. Top. Comput. 10(1): 137-156 (2022) - [j14]Shubham Rai
Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits. IEEE Trans. Emerg. Top. Comput. 10(2): 763-778 (2022) - [c26]Johann Knechtel, Jayanth Gopinath, Mohammed Ashraf, Jitendra Bhandari, Ozgur Sinanoglu, Ramesh Karri
Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest. ISPD 2022: 221-228 - [c25]Nikhil Rangarajan, Satwik Patnaik
SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture. ISVLSI 2022: 308-313 - [i30]Lilas Alrahis, Johann Knechtel, Florian Klemme, Hussam Amrouch, Ozgur Sinanoglu:
GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. CoRR abs/2208.02868 (2022) - [i29]Gino A. Chacon, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz:
Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems. CoRR abs/2210.00058 (2022) - [i28]Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young:
Security Closure of IC Layouts Against Hardware Trojans. CoRR abs/2211.07997 (2022) - [i27]Saideep Sreekumar, Mohammed Ashraf, Mohammed Nabeel, Ozgur Sinanoglu, Johann Knechtel:
X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks. CoRR abs/2211.08046 (2022) - [i26]Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu:
Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs. CoRR abs/2211.16495 (2022) - [i25]Shaza Elsharief, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu:
IsoLock: Thwarting Link-Prediction Attacks on Routing Obfuscation by Graph Isomorphism. IACR Cryptol. ePrint Arch. 2022: 1752 (2022) - 2021
- [j13]Haocheng Li
Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 1995-2008 (2021) - [j12]Satwik Patnaik
A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects. IEEE Trans. Emerg. Top. Comput. 9(4): 1815-1834 (2021) - [j11]Lilas Alrahis
UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking. IEEE Trans. Inf. Forensics Secur. 16: 2508-2523 (2021) - [c24]Johann Knechtel, Jayanth Gopinath, Jitendra Bhandari, Mohammed Ashraf, Hussam Amrouch, Shekhar Borkar, Sung Kyu Lim, Ozgur Sinanoglu, Ramesh Karri
Security Closure of Physical Layouts ICCAD Special Session Paper. ICCAD 2021: 1-9 - [c23]Jens Lienig, Susann Rothe
Toward Security Closure in the Face of Reliability Effects ICCAD Special Session Paper. ICCAD 2021: 1-9 - [c22]Johann Knechtel:
Hardware Security for and beyond CMOS Technology. ISPD 2021: 115-126 - [i24]Tapojyoti Mandal, Gino Chacon, Johann Knechtel, Ozgur Sinanoglu, Paul Gratz, Vassos Soteriou:
Interposer-Based Root of Trust. CoRR abs/2105.02917 (2021) - 2020
- [j10]Nikhil Rangarajan, Satwik Patnaik
SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory. IEEE Access 8: 76130-76142 (2020) - [j9]Johann Knechtel, Satwik Patnaik
Power Side-Channel Attacks in Negative Capacitance Transistor. IEEE Micro 40(6): 74-84 (2020) - [j8]Mohammed Nabeel, Mohammed Ashraf, Satwik Patnaik
2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets. IEEE Trans. Computers 69(11): 1611-1625 (2020) - [j7]Satwik Patnaik
Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1591-1606 (2020) - [j6]Satwik Patnaik
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4466-4481 (2020) - [c21]Johann Knechtel, Elif Bilge Kavun, Francesco Regazzoni, Annelie Heuser, Anupam Chattopadhyay, Debdeep Mukhopadhyay, Soumyajit Dey, Yunsi Fei
Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA. DATE 2020: 508-513 - [c20]Johann Knechtel:
Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges. ISPD 2020: 75-86 - [i23]Johann Knechtel:
Hardware Security for and beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges. CoRR abs/2001.08780 (2020) - [i22]Johann Knechtel, Elif Bilge Kavun, Francesco Regazzoni, Annelie Heuser, Anupam Chattopadhyay, Debdeep Mukhopadhyay, Soumyajit Dey, Yunsi Fei, Yaacov Belenky, Itamar Levi, Tim Güneysu, Patrick Schaumont, Ilia Polian:
Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA. CoRR abs/2001.09672 (2020) - [i21]Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel:
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. CoRR abs/2003.10830 (2020) - [i20]Johann Knechtel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Yogesh Singh Chauhan, Jörg Henkel, Ozgur Sinanoglu, Hussam Amrouch:
Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET). CoRR abs/2007.03987 (2020) - [i19]Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu:
Attacking Split Manufacturing from a Deep Learning Perspective. CoRR abs/2007.03989 (2020) - [i18]Mohammed Nabeel, Mohammed Ashraf, Satwik Patnaik, Vassos Soteriou, Ozgur Sinanoglu, Johann Knechtel:
2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets. CoRR abs/2009.02412 (2020) - [i17]Lilas Alrahis, Satwik Patnaik, Johann Knechtel, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu:
UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking. CoRR abs/2012.14938 (2020)
2010 – 2019
- 2019
- [j5]Nikhil Rangarajan
Spin-Based Reconfigurable Logic for Power- and Area-Efficient Applications. IEEE Des. Test 36(3): 22-30 (2019) - [c19]Johann Knechtel, Satwik Patnaik
Protect Your Chip Design Intellectual Property: An Overview. COINS 2019: 211-216 - [c18]Haocheng Li, Satwik Patnaik
Attacking Split Manufacturing from a Deep Learning Perspective. DAC 2019: 135 - [c17]Abhrajit Sengupta, Mohammed Nabeel, Johann Knechtel, Ozgur Sinanoglu
A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. DATE 2019: 414-419 - [c16]Johann Knechtel, Satwik Patnaik
3D Integration: Another Dimension Toward Hardware Security. IOLTS 2019: 147-150 - [i16]Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu:
Protect Your Chip Design Intellectual Property: An Overview. CoRR abs/1902.05333 (2019) - [i15]Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja:
SMART: Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory. CoRR abs/1902.07792 (2019) - [i14]Abhrajit Sengupta, Mohammed Thari Nabeel, Johann Knechtel, Ozgur Sinanoglu:
A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. CoRR abs/1903.02913 (2019) - [i13]Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja:
Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime. CoRR abs/1904.00421 (2019) - [i12]Mohammed Nabeel, Mohammed Ashraf, Satwik Patnaik, Vassos Soteriou
An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets. CoRR abs/1906.02044 (2019) - [i11]Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu:
3D Integration: Another Dimension Toward Hardware Security. CoRR abs/1906.02499 (2019) - [i10]Johann Knechtel, Jacek Gosciniak, Alabi Bojesomo, Satwik Patnaik, Ozgur Sinanoglu, Mahmoud Rasras:
Toward Physically Unclonable Functions from Plasmonics-Enhanced Silicon Disc Resonators. CoRR abs/1907.13229 (2019) - [i9]Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel:
A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects. CoRR abs/1908.03925 (2019) - 2018
- [j4]Johann Knechtel, Jens Lienig, Ibrahim Abe M. Elfadel
Multi-Objective 3D Floorplanning with Integrated Voltage Assignment. ACM Trans. Design Autom. Electr. Syst. 23(2): 22:1-22:27 (2018) - [c15]Satwik Patnaik
Concerted wire lifting: Enabling secure and cost-effective split manufacturing. ASP-DAC 2018: 251-258 - [c14]Sergii Osmolovskyi, Johann Knechtel, Igor L. Markov, Jens Lienig:
Optimal die placement for interposer-based 3D ICs. ASP-DAC 2018: 513-520 - [c13]Satwik Patnaik
Raise your game for split manufacturing: restoring the true functionality through BEOL. DAC 2018: 140:1-140:6 - [c12]Satwik Patnaik
Advancing hardware security using polymorphic and stochastic spin-hall effect devices. DATE 2018: 97-102 - [c11]Satwik Patnaik
Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs. ICCAD 2018: 8 - [i8]Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Ozgur Sinanoglu:
Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing. CoRR abs/1806.00787 (2018) - [i7]Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja:
Advancing Hardware Security Using Polymorphic and Stochastic Spin-Hall Effect Devices. CoRR abs/1806.00790 (2018) - [i6]Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu:
Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL. CoRR abs/1806.09135 (2018) - [i5]Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu, Shaloo Rakheja:
Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices. CoRR abs/1811.06012 (2018) - [i4]Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel:
Best of Both Worlds: Integration of Split Manufacturing and Camouflaging into a Security-Driven CAD Flow for 3D ICs. CoRR abs/1811.06822 (2018) - 2017
- [j3]Johann Knechtel, Ozgur Sinanoglu
Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration. IPSJ Trans. Syst. LSI Des. Methodol. 10: 45-62 (2017) - [c10]Johann Knechtel, Ozgur Sinanoglu
On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity. DAC 2017: 12:1-12:6 - [c9]Satwik Patnaik
Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging. ICCAD 2017: 41-48 - [c8]Abhrajit Sengupta, Satwik Patnaik
Rethinking split manufacturing: An information-theoretic approach with secure layout techniques. ICCAD 2017: 329-326 - [i3]Abhrajit Sengupta, Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Siddharth Garg, Ozgur Sinanoglu:
Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques. CoRR abs/1710.02026 (2017) - [i2]Johann Knechtel, Ozgur Sinanoglu:
On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity. CoRR abs/1710.02678 (2017) - [i1]Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu:
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. CoRR abs/1711.05284 (2017) - 2016
- [c7]Johann Knechtel, Jens Lienig:
Physical Design Automation for 3D Chip Stacks: Challenges and Solutions. ISPD 2016: 3-10 - 2015
- [j2]Johann Knechtel, Evangeline F. Y. Young, Jens Lienig:
Planning Massive Interconnects in 3-D Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1808-1821 (2015) - 2014
- [c6]Johann Knechtel, Evangeline F. Y. Young, Jens Lienig:
Structural planning of 3D-IC interconnects by block alignment. ASP-DAC 2014: 53-60 - 2013
- [c5]Puskar Budhathoki, Johann Knechtel, Andreas Henschel, Ibrahim Abe M. Elfadel
Integration of thermal management and floorplanning based on three-dimensional layout representations. ICECS 2013: 962-965 - [c4]Robert Fischbach
Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems. ISPD 2013: 11-16 - 2012
- [j1]Johann Knechtel, Igor L. Markov, Jens Lienig:
Assembling 2-D Blocks Into 3-D Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 228-241 (2012) - [c3]Johann Knechtel, Igor L. Markov, Jens Lienig, Matthias Thiele:
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration. ICCAD 2012: 705-712 - 2011
- [c2]Robert Fischbach
Investigating modern layout representations for improved 3d design automation. ACM Great Lakes Symposium on VLSI 2011: 337-342 - [c1]Johann Knechtel, Igor L. Markov, Jens Lienig:
Assembling 2D blocks into 3D chips. ISPD 2011: 81-88
Coauthor Index
[j27] [j26] [c36] [c35] [c34] [i41] [i40] [i39] [i37] [i36] [i35] [j25] [j24] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [i34] [i33] [i31] [j23] [j22] [j21] [j20] [j19] [j18] [j17] [j16] [j15] [j14] [c26] [c25] [i30] [i29] [i28] [i27] [i26] [i25] [j13] [j12] [j11] [c24] [c23] [i24] [j10] [j9] [j8] [j7] [j6] [i21] [i20] [i19] [i18] [i17] [j5] [c19] [c18] [c17] [c16] [i16] [i15] [i14] [i13] [i12] [i11] [i10] [i9] [c15] [c13] [c12] [c11] [i8] [i7] [i6] [i5] [i4] [j3] [c10] [c9] [c8] [i3] [i2] [i1]
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