A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL †
<p>Concept of split manufacturing, with splitting realized after M3 (without loss of generality). The FEOL by itself is missing the BEOL interconnects; hence, an FEOL-centric attacker has to infer those BEOL parts to obtain the full design.</p> "> Figure 2
<p>The classical threat model for split manufacturing, as also considered in this work. Red dashes mean the entity is untrusted (FEOL fab), whereas green dashes mean the entities are trusted (all others).</p> "> Figure 3
<p>Simple example for logic locking. (<b>a</b>) Original circuit; (<b>b</b>) locked circuit with one key-gate (correct key-bit is ‘0’).</p> "> Figure 4
<p>Physical design of the key for regular split manufacturing. (<b>a</b>) Locked layout, with key-nets connected to TIE cells, but following a regular, security-wise naive physical design. The placement of TIE cells, as well as the FEOL-level routing, can leave hints on the underlying assignment of key-bits to key-gates. (<b>b</b>) Locked layout of (<b>a</b>), with randomized placement of TIE cells. (<b>c</b>) Locked layout of (<b>b</b>), with key-nets lifted to the BEOL (i.e., above the split layer, which is M3 here). Note that lifting makes use of stacked vias to reduce FEOL-level routing and related hints to the bare minimum. (<b>d</b>) Locked layout of (<b>c</b>) after splitting. The broken key-nets are indecipherable for the FEOL-centric attacker.</p> "> Figure 5
<p>Physical design of the key for “poor man’s split manufacturing”. Instead of using TIE cells and requiring the related placement and routing to avoid any hints, this strategy here simply connects key-gates to I/O ports and bumps, which do not reveal any information by themselves. The key-bits can be implemented as fixed-value signals either (<b>a</b>) at a trusted packaging facility or (<b>b</b>) at the board level.</p> "> Figure 6
<p>Our physical design flow. After the synthesis stage, the flow is bifurcated into regular split manufacturing (SM) with lifting of key-nets to the BEOL versus “poor man’s split manufacturing” with lifting of key-nets to the package level. For the latter, TS cell is short for temporary cell, a custom cell we devise to enable lifting of nets to the package level.</p> "> Figure 7
<p>Randomized placement of TIE cells and key-nets lifted to the BEOL for benchmark b14_C, with M6 as split layer. For visibility in hard copies, colors are inverted. (<b>top</b>) Wiring of all key-nets, indicating that TIE cells and key-gates are decoupled. (<b>bottom</b>) A key-net highlighted. Routing is handled exclusively in M7 (green wire segments) and M8 (red segments).</p> "> Figure 8
<p>Layout costs for our scheme for various split layers. The respective baselines are the unprotected layouts. <span class="html-italic">Prelift</span> refers to locked layouts without lifting of key-nets. Each box comprises data points within the first and third quartile; the bar represents the median; the whiskers the minimum/maximum values; and outliers are marked by dots.</p> "> Figure 9
<p>Layout costs for our scheme for various split layers, and when using a single pair of TIE cells. The respective baselines are the unprotected layouts. <span class="html-italic">Prelift</span> refers to locked layouts without lifting of key-nets. Each box comprises data points within the first and third quartile, the bar represents the median; the whiskers; and the minimum/maximum values, and outliers are marked by dots.</p> "> Figure 10
<p>Layout and bump assignment for our case study on “poor man’s split manufacturing”, based on an ARM Cortex M0 core with various custom modules. (<b>top</b>) Design with lifting of 80 regular, single-fanout nets of the core. (<b>bottom</b>) Design with lifting of 80 key-nets, used to lock the core. Blue bumps are signal bumps and red/orange bumps are VDD/VSS bumps. Yellow flylines indicate the connectivity between bumps and the corresponding standard cells/pads. Recall that lifted nets are allowed to connect directly from cell to bump and vice versa. Most of the flylines radiate toward a region in the upper-right corner which is where the Cortex M0 core is placed.</p> ">
Abstract
:1. Introduction
1.1. Split Manufacturing and Its Threat Model
1.2. Proximity Attacks and Prior Work on Countermeasures
1.3. Motivation and Contributions
- A new paradigm for split manufacturing is proposed: lock the FEOL, unlock at the BEOL. The essence is to adapt the notion of logic locking to secure the layout and to explicitly route the nets holding the key through the BEOL (or even the package level).
- We define the security promise of split manufacturing and establish our paradigm with related proof.
- Based on this formal security analysis, we implement our paradigm without leaking any hints to foundry-based attackers, hindering any kind of proximity attacks. To that end, a CAD framework is developed for end-to-end implementation and evaluation of our scheme. The framework is based on commercial-grade tools and serves to (1) lock the FEOL by embedding key-gates into it, (2) implement the related key-bits using fixed-value signals and route the related key-nets through the BEOL (or even the package level), (3) control the layout cost, and (4) provide the split layouts for meaningful security evaluation. We release our framework and benchmarks publicly [17].
- Extensive experiments on ITC’99 and ISCAS benchmarks are carried out to demonstrate our scheme in terms of security and overhead. For an empirical security analysis, we leverage the state-of-the-art proximity attack in [18]. Besides, we further consider an “ideal proximity attack”, providing the most powerful analysis setup, which still cannot break our scheme. Further, the overhead for our scheme is marginal.
- We propose an alternative implementation which we call, in simple terms, “poor man’s split manufacturing”. This approach only requires a trusted packaging facility or even only board-level support, instead of a fully fledged and trusted back-end foundry. As it does not involve any splitting of the layout at all, the process for IP protection is streamlined in a less complicated and more practical way than traditional split manufacturing. We contrast “poor man’s split manufacturing” for regular IP protection versus our locking-inspired scheme, showing that ours is more practical.
2. Concept
2.1. Background and Threat Model
- For locking, the notion of an untrusted end-user forces the designer to store the key in a tamper-proof memory (TPM). Such TPMs remain an active area of research with their practicality and security still limited [21,22,23]. Further, these TPMs are fed to the circuit via flip/flops (FFs) that add complexity to the overall circuit design, as follows. First, these components can significantly increase the area footprint of a circuit; e.g., for [24], a single FF and the TPM part for a single bit incur 9 and 1.46 area, respectively, using the 65 nm GlobalFoundries LPe technology; for the baseline design, this would translate to up to 25% of the total area for the whole key. Second, the secure testability of these FFs poses a significant challenge for the designer [25,26,27]. In contrast, in our case where the threat model excludes possible attacks from end-users, the key-bits are implemented through so-called TIE cells (i.e., dedicated cells providing constant logic 0/1 signals) and the related key-nets are securely delegated to the BEOL or the package. As our technique neither requires a TPM nor any additional circuitry for key handling and testing, it does not hamper the overall complexity of the circuit.
- For ours, since chip fabrication is considered as currently ongoing (and, in any case, since the end-user is trusted), there is no physical chip copy available as an oracle, rendering oracle-guided attacks inapplicable.
2.2. Physical Embedding of the Key at the BEOL
2.2.1. Randomized Placement of TIE Cells
2.2.2. Lifting of Key-Nets
2.3. Physical Embedding of the Key at the Package Level: “Poor Man’s Split Manufacturing”
3. Formal Security Analysis
- 1.
- A split procedure is a function , where denotes the elements whose connections are complete, whereas denotes the elements which are left unconnected. contains the connectivity information for .
- 2.
- is outsourced to the FEOL facility, whereas is completed at a trusted BEOL/packaging facility, i.e., it remains the secret.
- 3.
- A circuit is compiled by completing connections on which can be viewed as a function such that .
- Physical proximity between TIE cells and key-gates, for regular split manufacturing, is dissolved by randomizing the placement of TIE cells. Again, such re-arrangement of TIE cells does not undermine the efficacy of any locking scheme of choice, given that TIE cells only provide the logical key-bit values, and do not carry any meaning beyond that. For connections between I/O ports and key-gates, for “poor man’s split manufacturing”, the notion of physical proximity is inapplicable. This is because the placement of I/O ports is independent of any gate placement, avoiding any correlation between proximity and connectivity.
- FEOL-level routing of key-nets for regular split manufacturing is controlled by lifting key-nets directly at the cells’ pins as a whole to the BEOL, using stacked vias both at the TIE cell’s output pin and at the key-gate’s input pin (Figure 4; also see Section 4). This way, any directional wiring which might otherwise leave hints is avoided to begin with. For FEOL-level routing to I/O ports, for “poor man’s split manufacturing”, the related directionality does not reveal any information by itself. Again, this is due to I/O port placement being independent of gate placement.
- Load capacitance constraints are neither applicable to TIE cells nor to I/O ports; both are no actual drivers.
- Combinational loops are absent from any key-net path by default, since TIE cells as well as I/O ports are not driven by any other gates themselves. Thus, avoiding loops for open nets cannot help an attacker rule out incorrect connections of key-nets.
- Timing constraints do not apply to TIE cells or I/O ports, as they define only static paths for key-nets.
4. Physical Design Framework
4.1. Synthesis for Logic Locking
4.2. Layout Generation for Regular Split Manufacturing
4.3. Layout Generation for “Poor Man’s Split Manufacturing”
5. Experimental Results
5.1. Security Analysis
5.2. Layout Analysis
5.3. Reducing the Number of TIE Cells
5.4. Discussions
5.5. “Poor Man’s Split Manufacturing”
6. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
References
- Follet, J. CRN Cisco Channel at Center of FBI Raid on Counterfeit Gear. 2018. Available online: www.crn.com/networking/207602683 (accessed on 12 March 2022).
- Xilinx V. Flextronics: Insight to a Gray Market. 2013. Available online: http://blog.optimumdesign.com/xilinx-v-flextronics-insight-to-a-gray-market (accessed on 12 March 2022).
- The Big Hack: How China Used a Tiny Chip to Infiltrate U.S. Companies. 2018. Available online: https://www.bloomberg.com/news/features/2018-10-04/the-big-hack-how-china-used-a-tiny-chip-to-infiltrate-america-s-top-companies (accessed on 12 March 2022).
- Innovation Is at Risk as Semiconductor Equipment and Materials Industry Loses up to $4 Billion Annually Due to IP Infringement. 2008. Available online: http://www.marketwired.com/press-release/innovation-is-risk-as-semiconductor-equipment-materials-industry-loses-up-4-billion-850034.htm (accessed on 12 March 2022).
- Detecting and Removing Counterfeit Semiconductors in the U.S. Supply Chain. 2013. Available online: https://www.semiconductors.org/clientuploads/directory/DocumentSIA/Anti%20Counterfeiting%20Task%20Force/ACTF%20Whitepaper%20Counterfeit%20One%20Pager%20Final.pdf (accessed on 12 March 2022).
- IARPA. IARPA Trusted Integrated Chips (TIC) Program. 2016. Available online: https://www.ndia.org/-/media/sites/ndia/meetings-and-events/divisions/systems-engineering/past-events/trusted-micro/2016-august/mccants-carl.ashx (accessed on 12 March 2022).
- Jarvis, R.; McIntyre, M. Split Manufacturing Method for Advanced Semiconductor Circuits. U.S. Patent 7,195,931, 27 March 2007. [Google Scholar]
- Hill, B.; Karmazin, R.; Otero, C.; Tse, J.; Manohar, R. A split-foundry asynchronous FPGA. In Proceedings of the Custom Integrated Circuits Conference, San Jose, CA, USA, 22–25 September 2013; pp. 1–4. [Google Scholar] [CrossRef] [Green Version]
- Vaidyanathan, K.; Das, B.P.; Sumbul, E.; Liu, R.; Pileggi, L. Building trusted ICs using split fabrication. In Proceedings of the International Symposium on Hardware-Oriented Security and Trust, Arlington, VA, USA, 6–7 May 2014; pp. 1–6. [Google Scholar]
- Rajendran, J.; Sinanoglu, O.; Karri, R. Is split manufacturing secure? In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 18–22 March 2013; pp. 1259–1264. [Google Scholar] [CrossRef]
- Jagasivamani, M.; Gadfort, P.; Sika, M.; Bajura, M.; Fritze, M. Split-fabrication obfuscation: Metrics and techniques. In Proceedings of the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Arlington, VA, USA, 6–7 May 2014; pp. 7–12. [Google Scholar] [CrossRef]
- Sengupta, A.; Patnaik, S.; Knechtel, J.; Ashraf, M.; Garg, S.; Sinanoglu, O. Rethinking split manufacturing: An information-theoretic approach with secure layout techniques. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Irvine, CA, USA, 13–16 November 2017; pp. 326–329. [Google Scholar]
- Imeson, F.; Emtenan, A.; Garg, S.; Tripunitara, M.V. Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation. In Proceedings of the USENIX Security Symposium, Washington, DC, USA, 14–16 August 2013; pp. 495–510. [Google Scholar]
- Magaña, J.; Shi, D.; Davoodi, A. Are Proximity Attacks a Threat to the Security of Split Manufacturing of Integrated Circuits? In Proceedings of the International Conference on Computer-Aided Design, Austin, TX, USA, 7–10 November 2016. [Google Scholar]
- Patnaik, S.; Knechtel, J.; Ashraf, M.; Sinanoglu, O. Concerted wire lifting: Enabling secure and cost-effective split manufacturing. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Jeju, Korea, 22–25 January 2018; pp. 251–258. [Google Scholar]
- Patnaik, S.; Ashraf, M.; Knechtel, J.; Sinanoglu, O. Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL. In Proceedings of the ACM/ESDA/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 24–28 June 2018; pp. 140:1–140:6. [Google Scholar]
- Sengupta, A.; Nabeel, M.; Ashraf, M. Poor Man’s Split Manufacturing. GitHub. 2022. Available online: https://github.com/DfX-NYUAD/Poor-Man-s-Split-Manufacturing (accessed on 12 March 2022).
- Wang, Y.; Chen, P.; Hu, J.; Li, G.; Rajendran, J. The Cat and Mouse in Split Manufacturing. Trans. VLSI Syst. 2018, 26, 805–817. [Google Scholar] [CrossRef]
- Roy, J.A.; Koushanfar, F.; Markov, I.L. Ending Piracy of Integrated Circuits. Computer 2010, 43, 30–38. [Google Scholar] [CrossRef]
- Sengupta, A.; Nabeel, M.; Limaye, N.; Ashraf, M.; Sinanoglu, O. Truly Stripping Functionality for Logic Locking: A Fault-based Perspective. Trans. Comp.-Aided Des. Integ. Circ. Syst. 2020, 39, 4439–4452. [Google Scholar] [CrossRef]
- Tuyls, P.; Schrijen, G.J.; Škorić, B.; van Geloven, J.; Verhaegh, N.; Wolters, R. Read-Proof Hardware from Protective Coatings. In Proceedings of the Cryptographic Hardware and Embedded Systems, Yokohama, Japan, 10–13 October 2006; pp. 369–383. [Google Scholar]
- Anceau, S.; Bleuet, P.; Clédière, J.; Maingault, L.; Rainard, J.l.; Tucoulou, R. Nanofocused X-Ray Beam to Reprogram Secure Circuits. In Proceedings of the Cryptographic Hardware and Embedded Systems, Taipei, Taiwan, 25–28 September 2017; pp. 175–188. [Google Scholar]
- Courbon, F.; Skorobogatov, S.; Woods, C. Direct charge measurement in Floating Gate transistors of Flash EEPROM using Scanning Electron Microscopy. In Proceedings of the International Symposium for Testing and Failure Analysis, Fort Worth, TX, USA, 6–10 November 2016; pp. 1–9. [Google Scholar]
- Sengupta, A.; Nabeel, M.; Yasin, M.; Sinanoglu, O. ATPG-based cost-effective, secure logic locking. In Proceedings of the VLSI Test Symposium (VTS), San Francisco, CA, USA, 22–25 April 2018; pp. 1–6. [Google Scholar]
- Guin, U.; Zhou, Z.; Singh, A. Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test. IEEE Trans. Very Large Scale Integr. Syst. 2018, 26, 818–830. [Google Scholar] [CrossRef]
- Limaye, N.; Sengupta, A.; Nabeel, M.; Sinanoglu, O. Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access. In Proceedings of the International Conference on Computer-Aided Design (ICCAD), Westminster, CO, USA, 4–7 November 2019; pp. 1–8. [Google Scholar]
- Limaye, N.; Sinanoglu, O. DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 9–13 March 2020; pp. 270–273. [Google Scholar]
- Engels, S.; Hoffmann, M.; Paar, C. The End of Logic Locking? A Critical View on the Security of Logic Locking. Cryptology ePrint Archive, Report 2019/796. 2019. Available online: https://eprint.iacr.org/2019/796 (accessed on 12 March 2022).
- Rahman, M.T.; Tajik, S.; Rahman, M.S.; Tehranipoor, M.; Asadizanjani, N. The Key is Left under the Mat: On the Inappropriate Security Assumption of Logic Locking Schemes. 2019. Available online: https://eprint.iacr.org/2019/719 (accessed on 12 March 2022).
- Rahman, M.T.; Rahman, M.S.; Wang, H.; Tajik, S.; Khalil, W.; Farahmandi, F.; Forte, D.; Asadizanjani, N.; Tehranipoor, M. Defense-in-Depth: A Recipe for Logic Locking to Prevail. arXiv 2019, arXiv:1907.08863. [Google Scholar] [CrossRef] [Green Version]
- Lippmann, B.; Unverricht, N.; Singla, A.; Ludwig, M.; Werner, M.; Egger, P.; Duebotzky, A.; Graeb, H.; Gieser, H.; Rasche, M.; et al. Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies. Integration 2020, 71, 11–29. [Google Scholar] [CrossRef]
- Wahby, R.S.; Howald, M.; Garg, S.; Walfish, M. Verifiable ASICs. In Proceedings of the Symposium on Security and Privacy (SP), San Jose, CA, USA, 22–26 May 2016; pp. 759–778. [Google Scholar]
- Nabeel, M.; Ashraf, M.; Patnaik, S.; Soteriou, V.; Sinanoglu, O.; Knechtel, J. 2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets. Trans. Comp. 2020, 69, 1611–1625. [Google Scholar] [CrossRef]
- List of Semiconductor Fabrication Plants. 2020. Available online: https://en.wikipedia.org/wiki/List_of_semiconductor_fabrication_plants (accessed on 12 March 2022).
- Brinton, J.B.; Lineback, B.J.R. Packaging Is Becoming Biggest Cost in Assembly, Passing Capital Equipment. 1999. Available online: https://www.eetimes.com/packaging-is-becoming-biggest-cost-in-assembly-passing-capital-equipment/ (accessed on 12 March 2022).
- Kanellos, M. Intel Plans Chip Packaging Center in China. 2003. Available online: https://www.cnet.com/news/intel-plans-chip-packaging-center-in-china/ (accessed on 12 March 2022).
- Smart, N. ECRYPT II Yearly Report on Algorithms and Keysizes (2011–2012). 2012. Available online: http://www.ecrypt.eu.org/ecrypt2/documents/D.SPA.20.pdf (accessed on 12 March 2022).
- Subramanyan, P.; Ray, S.; Malik, S. Evaluating the security of logic encryption algorithms. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, USA, 5–7 May 2015; pp. 137–143. [Google Scholar] [CrossRef]
- NanGate FreePDK45 Open Cell Library. 2011. Available online: http://www.nangate.com/?page_id=2325 (accessed on 12 March 2022).
- Wang, Y.; Chen, P.; Hu, J.; Rajendran, J. Routing Perturbation for Enhanced Security in Split Manufacturing. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, 16–19 January 2017; pp. 605–610. [Google Scholar]
M1 | M2 | M3 | M4 | M5 | M6 | M7 | M8 | M9 | M10 |
---|---|---|---|---|---|---|---|---|---|
70 | 70 | 70 | 140 | 140 | 140 | 400 | 400 | 800 | 800 |
Benchmark | M4 | M6 | ||||
---|---|---|---|---|---|---|
Key-Nets | Regular | Key-Nets | Regular | |||
Logical | Physical | Nets | Logical | Physical | Nets | |
b14 | 50 | 1.8 | 18.5 | 48.4 | 0.9 | 25.3 |
b15 | 49.6 | 0 | 24.5 | 48.4 | 0.9 | 32 |
b17 | NA | NA | NA | 49.2 | 0 | 24.5 |
b20 | 47.6 | 0.9 | 17.7 | 49.9 | 1.8 | 31.0 |
b21 | 47.8 | 0 | 14.8 | 48.3 | 0 | 31.8 |
b22 | 49.4 | 0 | 16.8 | 48.5 | 0 | 36.3 |
Average | 48.9 | 0.5 | 18.4 | 48.8 | 0.6 | 30.2 |
Benchmark | M4 | M6 | ||
---|---|---|---|---|
HD | OER | HD | OER | |
b14 | 34.3 | 100 | 13.0 | 100 |
b15 | 38.5 | 100 | 15.9 | 100 |
b17 | NA | NA | 26.4 | 100 |
b20 | 41.1 | 100 | 18.7 | 100 |
b21 | 42.7 | 100 | 24.4 | 100 |
b22 | 41.9 | 100 | 22.4 | 100 |
Average | 39.7 | 100 | 20.1 | 100 |
Benchmark | [40] | [15] | [16] | Proposed | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PNR | CCR | HD | OER | PNR | CCR | HD | OER | PNR | CCR | HD | OER | PNR | CCR | HD | OER | |
c432 | 87.5 | 78.8 | 46.1 | 99.4 | 32.3 | 0 | 45.9 | 100 | NA | 0 | 48.4 | 99.9 | 13.1 | 3.7 | 39.5 | 98.9 |
c880 | 86.8 | 45.8 | 18.0 | 99.9 | 28.3 | 0 | 39.9 | 100 | NA | 0 | 43.4 | 99.9 | 16.8 | 0 | 38.7 | 100 |
c1355 | 84.9 | 77.1 | 26.6 | 100 | 32.8 | 0 | 46.1 | 100 | NA | 0 | 40.1 | 99.9 | 10.2 | 3.4 | 41.4 | 100 |
c1908 | 91.2 | 83.8 | 38.8 | 100 | 29.5 | 0 | 48.1 | 100 | NA | 0 | 46.2 | 99.9 | 9.9 | 2.7 | 33.7 | 100 |
c3540 | 86.2 | 77.0 | 36.1 | 100 | 30.8 | 0 | 46.4 | 100 | NA | 0 | 47.9 | 99.9 | 8.3 | 0 | 40.8 | 100 |
c5315 | 87.7 | 74.7 | 18.1 | 100 | 31.6 | 0 | 35.4 | 100 | NA | 0 | 38.3 | 99.9 | 21.7 | 1.6 | 23.8 | 100 |
c7552 | 93.9 | 73.9 | 20.3 | 100 | 26.9 | 0 | 25.7 | 100 | NA | 0 | 27.8 | 99.9 | 26.2 | 0.9 | 24.1 | 100 |
Average | 88.3 | 73.3 | 29.1 | 99.9 | 30.3 | 0 | 41.1 | 100 | NA | 0 | 41.7 | 99.9 | 15.2 | 1.8 | 34.6 | 99.8 |
Benchmark | M4 | M6 | M8 | ||||||
---|---|---|---|---|---|---|---|---|---|
Key Nets | Regular Nets | Key Nets | Regular Nets | Key Nets | Regular Nets | ||||
Logical | Physical | Logical | Physical | Logical | Physical | ||||
b14 | 47.9 | 1.1 | 49.5 | 44.2 | 8.8 | 23.2 | 37.5 | 25.3 | 11.7 |
b15 | 46.1 | 0.9 | 23.1 | 47.6 | 1.8 | 33.8 | 45.8 | 2.7 | 23.2 |
b17 | NA | NA | NA | 44.8 | 8.7 | 23.6 | 45.2 | 5.2 | 36.1 |
b20 | 16.9 | 0 | 27.4 | 47.8 | 0 | 49.2 | 43.6 | 6.6 | 38.8 |
b21 | 45.5 | 1.9 | 23.9 | 47.7 | 2.8 | 45.4 | 42.7 | 9.4 | 40.5 |
b22 | 46.1 | 6.5 | 48.8 | 45.5 | 6.5 | 48.8 | 43.8 | 10.8 | 28.4 |
Average | 46.5 | 2.1 | 34.5 | 46.3 | 4.8 | 37.3 | 43.1 | 10.0 | 29.8 |
Benchmark | M4 | M6 | M8 | |||
---|---|---|---|---|---|---|
HD | OER | HD | OER | HD | OER | |
b14 | 21.9 | 100 | 9.7 | 100 | 7.7 | 100 |
b15 | 39.0 | 100 | 15.3 | 100 | 6.8 | 100 |
b17 | NA | NA | 23.2 | 100 | 7.2 | 100 |
b20 | 37.9 | 100 | 18.5 | 100 | 4.8 | 100 |
b21 | 39.7 | 100 | 11.3 | 100 | 4.5 | 100 |
b22 | 37.2 | 100 | 11.9 | 100 | 6.3 | 100 |
Average | 35.1 | 100 | 16.0 | 100 | 6.2 | 100 |
Key-Size (%) | 5 | 10 | 15 | 20 | 25 |
---|---|---|---|---|---|
HD / OER (%) | 15.0/100 | 24.0/100 | 31.0/100 | 36.5/100 | 39.7/100 |
Split Layer | M1 | M2 | M3 | M4 | M5 | M6 | M7 | M8 |
---|---|---|---|---|---|---|---|---|
Logical CCR | 49.9 | 48.6 | 49.6 | 49.9 | 48.6 | 49.0 | 49.2 | 49.2 |
Metric/Design Case | Regular Nets Lifted | Key-Nets Lifted |
---|---|---|
Timing Cost | 423% | 0% |
Die-Area Cost | 0% | 0% |
Power Cost | 3.12% | 1.56% |
Lifted Nets | 80 | 80 |
Bumps: Lifted S.S./Total | 160/181 | 80/101 |
Bump: Power/Total | 44/225 | 95/196 |
Bump Spacing | 200 μm | 225 μm |
Timing Constraint | 15 ns | 15 ns |
Utilization Rate | 0.6 | 0.6 |
Gates | ≈180 K | ≈180 K |
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Sengupta, A.; Nabeel, M.; Ashraf, M.; Knechtel, J.; Sinanoglu, O. A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. Cryptography 2022, 6, 22. https://doi.org/10.3390/cryptography6020022
Sengupta A, Nabeel M, Ashraf M, Knechtel J, Sinanoglu O. A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. Cryptography. 2022; 6(2):22. https://doi.org/10.3390/cryptography6020022
Chicago/Turabian StyleSengupta, Abhrajit, Mohammed Nabeel, Mohammed Ashraf, Johann Knechtel, and Ozgur Sinanoglu. 2022. "A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL" Cryptography 6, no. 2: 22. https://doi.org/10.3390/cryptography6020022